Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
Table 4-25. PCI, HPI, EMIFA, and ATA Pin Muxing (continued)
PIN FUNCTIONS (WITH PCIEN, HPIEN, ATAEN VALUES)
1xx
(1)
010 011 000 001
PCI_AD26 HD26 DD10 EM_A[10] DD10
PCI_AD25 HD25 DD9 EM_A[9] DD9
PCI_AD24 HD24 DD8 EM_A[8] DD8
PCI_AD23 HD23 DD7 EM_A[7] DD7
PCI_AD22 HD22 DD6 EM_A[6] DD6
PCI_AD21 HD21 DD5 EM_A[5] DD5
PCI_AD20 HD20 DD4 EM_A[4] DD4
PCI_AD19 HD19 DD3 EM_A[3] DD3
PCI_AD18 HD18 DD2 EM_A[2] DD2
PCI_AD17 HD17 DD1 EM_A[1] DD1
PCI_AD16 HD16 DD0 EM_A[0] DD0
PCI_AD15 HD15 HD15 EM_D15 EM_D15
PCI_AD14 HD14 HD14 EM_D14 EM_D14
PCI_AD13 HD13 HD13 EM_D13 EM_D13
PCI_AD12 HD12 HD12 EM_D12 EM_D12
PCI_AD11 HD11 HD11 EM_D11 EM_D11
PCI_AD10 HD10 HD10 EM_D10 EM_D10
PCI_AD9 HD9 HD9 EM_D9 EM_D9
PCI_AD8 HD8 HD8 EM_D8 EM_D8
PCI_AD7 HD7 HD7 EM_D7 EM_D7
PCI_AD6 HD6 HD6 EM_D6 EM_D6
PCI_AD5 HD5 HD5 EM_D5 EM_D5
PCI_AD4 HD4 HD4 EM_D4 EM_D4
PCI_AD3 HD3 HD3 EM_D3 EM_D3
PCI_AD2 HD2 HD2 EM_D2 EM_D2
PCI_AD1 HD1 HD1 EM_D1 EM_D1
PCI_AD0 HD0 HD0 EM_D0 EM_D0
PCI_RST GP[13] DA2 EM_A[22] DA2
PCI_RSV0
(2)
GP[16] DA1 EM_A[21] DA1
PCI_RSV1
(2)
GP[17] DA0 EM_A[20] DA0
PCI_RSV2
(2)
GP[18] INTRQ EM_RSV0 INTRQ
PCI_RSV3
(2)
GP[19] DIOR EM_WAIT5/(RDY5/BSY5) DIOR
PCI_RSV4
(2)
GP[20] DIOW EM_WAIT4/(RDY4/BSY4) DIOW
PCI_RSV5
(2)
GP[21] IORDY EM_WAIT3/(RDY3/BSY3) IORDY
(2) In PCI mode (PCIEN = 1), the internal pullups/pulldowns (IPUs/IPDs) are disabled on all PCI pins and it is recommended to have
external pullup resistors on the PCI_RSV[5:0] pins. For more detailed information on external pullup/pulldown resistors, see
Section 4.8.1, Pullup/Pulldown Resistors.
114 Device Configurations Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320DM6467T