Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
Table 4-22. PINMUX0 Register Bit Descriptions
BIT NAME DESCRIPTION
This bit disables USB_DRVVBUS output.
31 VBUSDIS 0 = USB_DRVVBUS function selected.
1 = GP[22] function selected.
This bit enables STC Source Clock input.
30 STCCK 0 = GP[4] function selected.
1 = STC_CLKIN function selected.
This bit enables AUDIO_CLK1 output.
29 AUDCK1 0 = GP[2] function selected.
1 = AUDIO_CLK1 function selected.
This bit enables AUDIO_CLK0 output.
28 AUDCK0 0 = GP[3] function selected.
1 = AUDIO_CLK0 function selected.
27 RSV Reserved. Read returns "0".
CRGEN Pin Mux Control (see Section 4.7.3.7, CRGEN Signal Muxing).
000 = No CRGEN signals enabled.
001 = CRGEN1 selection enabled (muxed with UART2 data).
010 = Reserved (no CRGEN signals enabled).
26:24 CRGMUX 011 = Reserved (no CRGEN signals enabled).
100 = CRGEN0 selection enabled (muxed with UCTS2 and PWM0).
101 = CRGEN0 and CRGEN1 selection enabled.
110 = CRGEN0 selection enabled (muxed with UART2 data).
111 = Reserved (no CRGEN signals enabled).
TSIF1 Serial Output Pin Mux Control (see
(1)
, TSSO Signal Muxing).
0x = No TS1 output signals enabled.
23:22 TSSOMUX
10 = TS1 output selection enabled (muxed on VP_DOUT pins).
11 = TS1 output selection enabled (muxed on URIN0, UCTS2, PWM0, and PWM1 pins).
TSIF1 Serial Input Pin Mux Control (see Section 4.7.3.5, TSIF1 Input Signal Muxing).
00 = No TS1 input signals enabled.
21:20 TSSIMUX 01 = TS1 input selection enabled (muxed on UART0 pins).
10 = TS1 input selection enabled (muxed on VP_DOUT pins).
11 = TS1 input selection enabled (muxed on VP_DIN pins).
TSIF0 Parallel/Serial Output Pin Mux Control (see Section 4.7.3.4, TSIF0 Output Signal Muxing).
0x = No TS0 output signals enabled.
19:18 TSPOMUX
10 = TS0 parallel output muxing enabled (muxed with VP_DIN pins).
11 = TS0 serial output muxing enabled (muxed TS0_DOUT7 with UTXD1).
TSIF0 Parallel/Serial Input Pin Mux Control (see Section 4.7.3.3, TSIF0 Input Signal Muxing).
0x = No TS0 signals enabled.
17:16 TSPIMUX
10 = TS0 parallel input muxing enabled (muxed with VP_DIN pins).
11 = TS0 serial input muxing enabled (muxed TS0_DIN7 with URXD1).
15:6 RESERVED Reserved. Read returns "0".
Reserved. Read returns "0". Note: For proper device operation, when writing to this bit, only a "0"
5 RESERVED
should be written.
4:3 RESERVED Reserved. Read returns "0".
PCI Function Enable (see Section 4.7.3.1, PCI, HPI, EMIFA and ATA Pin Muxing).
2 PCIEN
Default value is determined by PCIEN boot configuration pin.
1 HPIEN HPI Function Enable (see Section 4.7.3.1, PCI, HPI, EMIFA and ATA Pin Muxing).
0 ATAEN ATA Function Enable (see Section 4.7.3.1, PCI, HPI, EMIFA and ATA Pin Muxing).
(1) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
Copyright © 2009–2012, Texas Instruments Incorporated Device Configurations 111
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