Datasheet

Table Of Contents
TMS320DM6467T
www.ti.com
SPRS605C JULY 2009REVISED JUNE 2012
4.5.4 DSPBOOT
The DSPBOOT input determines DSP operation at reset. For most applications, the ARM is the master
device and controls the reset and boot of the DSP. Under this scenario (DSPBOOT = 0), the DSP will
remain disabled (held in reset) after reset. The ARM is responsible for releasing DSP from reset. Before
releasing DSP from reset, the ARM must transfer a valid DSP boot image to program memory accessible
by the DSP (DSP memory, EMIFA or DDR2), and configure the DSP boot address in DSPBOOTADDR
register (in SYSTEM module) from which the DSP will begin execution.
When DSPBOOT = 1, the DSP will boot itself. Under this scenario, DSP will be released from reset
without ARM intervention. The DSP boot address is set to an EMIFA address 0x4220 0000h. DSP will
begin execution with instruction (L1P) cache enabled.
Note: The DSPBOOT operation is overridden when ARM HPI or PCI boot is selected (BTMODE[3:0] =
001x). This is because ARM HPI/PCI boot selection will force the HPIEN or PCIEN bit in PINMUX0 to ‘1’.
This enables UHPI/PCI functions on the EMIFA control and data pins and prevents the DSP from using
EMIFA. DSPBOOT is treated as "0" internally when BTMODE[3:0] = 001x, regardless of the value at the
configuration pin (The actual pin value should still be latched in the BOOTCFG register of the System
Module).
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