Datasheet

TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012 www.ti.com
Table 4-13. Default Functions Affected by Device Boot and Configuration Pins (continued)
DEVICE BOOT AND
BOOT SELECTED PIN MUX CONTROL GLOBAL SETTING PERIPHERAL SETTING
CONFIGURATION PINS
DSPBOOT Bit = 0, DSP is booted by – – Note: that either NOR
the ARM Flash or ROM must be
Bit =1, DSP boots self connected to the first
from EMIFA EMIFA chip select space
(CS2).
The EMIFA does not
support direct execution
from NAND Flash. Code
within the EMIFA memory
should execute a branch
to the actual EMIFA
address and then disable
the Instruction Address
Modification logic (by
clearing the ADDRMOD
bit in the ARMBOOT
register of the System
Module).
For proper device operation, external pullup/pulldown resistors may be required on these device boot and
configuration pins. For discussion situations where external pullup/pulldown resistors are required, see
Section 4.8.1, Pullup/Pulldown Resistors.
Note: All DM6467T device configuration inputs (BOOTMODE[3:0], CS2BW, PCIEN, and DSPBOOT) are
multiplexed with other functional pins. These pins function as device boot and configuration pins only
during device reset. The user must take care of any potential data contention in the system. To help avoid
system data contention, the DM6467T puts these configuration pins into a high-impedance state (Hi-Z)
when device reset (RESET or POR) is asserted, and continues to hold them in a high-impedance state
until the internal global reset is removed; at which point, the default peripheral (VPIF) will now control
these pins.
All of the device boot and configuration pin settings are captured in the corresponding bit fields in the
BOOTCFG register (see Section 4.4.2.3).
The following subsections provide more details on the device configurations determined at device reset:
CS2BW, PCIEN, and DSPBOOT.
4.5.2 EMIFA CS2 Bus Width (CS2BW)
The default width of the first EMIFA chip select space (CS2) is determined by the CS2BW value. If
CS2BW = 0, the space defaults to 8-bits wide. If CS2BW = 1, it defaults to 16-bits wide. This allows the
ARM to make full use of the width of the attached memory device when booting from EMIFA.
Note: CS2BW only selects the default bus width. The EMIFA bus width may be changed at any time via
software by accessing the appropriate EMIFA control register.
The default width affects only the first chip select space (CS2). All other chip select spaces default to 8-
bits wide and must be modified using the appropriate EMIFA control register if 16-bit operation is desired.
4.5.3 PCI Enable (PCIEN)
The PCIEN configuration pin determines if the PCI peripheral is used on this device. If PCIEN = 1
indicating the PCI is used, then the PCI multiplexed pins default to PCI functions, and the pins’
corresponding internal pullup/pulldown resistors are disabled. If PCIEN = 0 indicating the PCI is not used,
then the PCI muxed pins default to non-PCI functions (e.g., EMIFA or HPI pin functions), and the pins’
corresponding internal pullup/pulldown resistors are enabled.
The PCIEN setting is captured and stored in the BOOTCFG.PCIEN bit field, and also in the
PINMUX0.PCIEN bit field.
100 Device Configurations Copyright © 2009–2012, Texas Instruments Incorporated
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