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TMS320DM6467T

www.ti.com

SPRS605C –JULY 2009–REVISED JUNE 2012

TMS320DM6467T

Digital Media System-on-Chip

Check for Samples: TMS320DM6467T

1 Digital Media System-on-Chip (DMSoC)

1.1 Features

– 128K-Byte L2 Unified Mapped RAM/Cache

• High-Performance Digital Media SoC

(Flexible RAM/Cache Allocation)

– 1-GHz C64x+™ Clock Rate

• ARM926EJ-S Core

– 500-MHz ARM926EJ-S™ Clock Rate

– Support for 32-Bit and 16-Bit (Thumb®

– Eight 32-Bit C64x+ Instructions/Cycle

Mode) Instruction Sets

– 8000 C64x+ MIPS

– DSP Instruction Extensions and Single Cycle

– Fully Software-Compatible With C64x /

MAC

ARM9™

– ARM® Jazelle® Technology

– Industrial Temperature Devices Available

– EmbeddedICE-RT™ Logic for Real-Time

• Advanced Very-Long-Instruction-Word (VLIW)

Debug

TMS320C64x+™ DSP Core

• ARM9 Memory Architecture

– Eight Highly Independent Functional Units

– 16K-Byte Instruction Cache

• Six ALUs (32-/40-Bit), Each Supports

– 8K-Byte Data Cache

Single 32-Bit, Dual 16-Bit, or Quad 8-Bit

– 32K-Byte RAM

Arithmetic per Clock Cycle

– 8K-Byte ROM

• Two Multipliers Support Four 16 x 16-Bit

Multiplies (32-Bit Results) per Clock • Embedded Trace Buffer™ (ETB11™) With 4KB

Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Memory for ARM9 Debug

Results) per Clock Cycle

• Endianness: Little Endian for ARM and DSP

– Load-Store Architecture With Non-Aligned

• Dual Programmable High-Definition Video

Support

Image Co-Processor (HDVICP) Engines

– 64 32-Bit General-Purpose Registers

– Supports a Range of Encode, Decode, and

– Instruction Packing Reduces Code Size Transcode Operations

– All Instructions Conditional • H.264, MPEG2, VC1, MPEG4 SP/ASP

– Additional C64x+™ Enhancements • 150-MHz Video Port Interface (VPIF)

• Protected Mode Operation – Two 8-Bit SD (BT.656), Single 16-Bit HD

(BT.1120), or Single Raw (8-/10-/12-Bit) Video

• Exceptions Support for Error Detection

Capture Channels

and Program Redirection

– Two 8-Bit SD (BT.656) or Single 16-Bit HD

• Hardware Support for Modulo Loop

(BT.1120) Video Display Channels

Operation

• Video Data Conversion Engine (VDCE)

• C64x+ Instruction Set Features

– Horizontal and Vertical Downscaling

– Byte-Addressable (8-/16-/32-/64-Bit Data)

– Chroma Conversion (4:2:2↔4:2:0)

– 8-Bit Overflow Protection

• Two Transport Stream Interface (TSIF) Modules

– Bit-Field Extract, Set, Clear

(One Parallel/Serial and One Serial Only)

– Normalization, Saturation, Bit-Counting

– TSIF for MPEG Transport Stream

– Compact 16-Bit Instructions

– Simultaneous Synchronous or

– Additional Instructions to Support Complex

Asynchronous Input/Output Streams

Multiplies

– Absolute Time Stamp Detection

• C64x+ L1/L2 Memory Architecture

– PID Filter With 7 PID Filter Tables

– 32K-Byte L1P Program RAM/Cache (Direct

– Corresponding Clock Reference Generator

Mapped)

(CRGEN) Modules for System Time-Clock

– 32K-Byte L1D Data RAM/Cache (2-Way Set-

Recovery

Associative)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Summary of content (352 pages)

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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 TMS320DM6467T Digital Media System-on-Chip Check for Samples: TMS320DM6467T 1 Digital Media System-on-Chip (DMSoC) 1.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com • External Memory Interfaces (EMIFs) – Up to 400-MHz 32-Bit DDR2 SDRAM Memory Controller With 512M-Byte Address Space (1.8-V I/O) – Asynchronous16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach • Flash Memory Interfaces – NOR (8-/16-Bit-Wide Data) – NAND (8-/16-Bit-Wide Data) • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) – Programmable Default Burst Size • 10/100/1000 Mb/s Ethernet MAC (EMAC) – IEEE 802.
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TMS320DM6467T www.ti.com 1.2 SPRS605C – JULY 2009 – REVISED JUNE 2012 Description The TMS320DM6467T (also referenced as DM6467T) leverages TI’s DaVinci™ technology to meet the networked media encode and decode digital media processing needs of next-generation embedded devices.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com interrupt/event generation modes, multiplexed with other peripherals; 3 UART/IrDA/CIR interfaces with modem interface signals on UART0; 2 pulse width modulator (PWM) peripherals; an ATA/ATAPI-6 interface; a 66-MHz peripheral component interface (PCI); and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.
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TMS320DM6467T www.ti.com 1.3 SPRS605C – JULY 2009 – REVISED JUNE 2012 Functional Block Diagram Figure 1-1 shows the functional block diagram of the device.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 1 Digital Media System-on-Chip (DMSoC) ............ 1 ............................................. 1 1.2 Description ........................................... 3 1.3 Functional Block Diagram ........................... 5 Revision History ........................................ 7 Device Overview ........................................ 8 3.1 Device Characteristics ............................... 8 3.2 Device Compatibility ..........................
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 2 Revision History This data manual revision history highlights the technical changes made to the SPRS605B devicespecific data manual to make it an SPRS605C revision. Scope: Applicable updates to the DM646x DMSoC device family, specifically relating to the TMS320DM6467 device (all Silicon Revisions 3.0, 1.1, and 1.0) which is now in teh production data (PD) stage of development have been incorporated.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 3 Device Overview 3.1 Device Characteristics Table 3-1 provides an overview of the TMS320DM6467T SoC. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the C64x+ DSP, and the package type with pin count. Table 3-1.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-1. Characteristics of the DM6467T Processor (continued) HARDWARE FEATURES DM6467T Size (Bytes) On-Chip Memory 248KB RAM, 8KB ROM DSP • 32KB L1 Program (L1P)/Cache (up to 32KB) • 32KB L1 Data (L1D)/Cache (up to 32KB) • 128KB Unified Mapped RAM/Cache (L2) Organization ARM • 16KB I-cache • 8KB D-cache • 32KB RAM • 8KB ROM CPU ID + CPU Rev ID Control Status Register (CSR.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 3.2 www.ti.com Device Compatibility The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc. The C64x+ DSP core is code-compatible with the C6000™ DSP platform and supports features of the C64xT DSP family. 3.3 ARM Subsystem The ARM Subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available at http://www.arm.com 3.3.2 CP15 The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and other ARM subsystem functions.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 3.3.5 www.ti.com Tightly Coupled Memory (TCM) ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt Vector table. ARM internal ROM enables non-EMIFA boot options, such as NAND and UART. The RAM and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides for separate instruction and data bus connections.
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TMS320DM6467T www.ti.com 3.3.8.3 SPRS605C – JULY 2009 – REVISED JUNE 2012 DSP Memories The ARM has access to the following DSP memories: • L2 RAM • L1P RAM • L1D RAM 3.3.8.4 ARM-DSP Integration DM6467T ARM and DSP integration features are as follows: • DSP visibility from ARM’s memory map, see Section 3.5, Memory Map Summary, for details • Boot Modes for DSP - see Device Configurations section, Section 4.4.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 3.3.13 System Module The ARM Subsystem includes the System module. The System module consists of a set of registers for configuring and controlling a variety of system functions. For details and register descriptions for the System module, see Section 4, Device Configurations and see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number SPRUEP9). 3.3.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions. The C64x+ core enhances the .S unit in several ways.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 Á ÁÁ Á Á Á ÁÁ Á ÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á www.ti.com src1 Odd register file A (A1, A3, A5...A31) src2 .L1 odd dst Even register file A (A0, A2, A4...A30) (D) even dst long src ST1b ST1a 32 MSB 32 LSB long src 8 8 even dst odd dst .S1 src1 Data path A (D) src2 LD1b LD1a 32 LSB DA2 32 32 src2 32 MSB DA1 LD2a LD2b Á Á Á Á Á Á .M1 dst2 dst1 src1 (A) (B) (C) dst .
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TMS320DM6467T www.ti.com 3.4.2 SPRS605C – JULY 2009 – REVISED JUNE 2012 DSP Memory Mapping The DSP memory map is shown in Section 3.5, Memory Map Summary. Configuration of the control registers for DDR2, EMIFA, and ARM Internal RAM is supported by the ARM. The DSP has access to memories shown in the following sections. 3.4.2.1 ARM Internal Memories The DSP has access to the 32KB ARM Internal RAM on the ARM D-TCM interface (i.e., data only). 3.4.2.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-2.
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TMS320DM6467T www.ti.com 3.5 SPRS605C – JULY 2009 – REVISED JUNE 2012 Memory Map Summary Table 3-3 shows the memory map address ranges of the device. Table 3-4 depicts the expanded map of the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories associated with its two processors and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-3.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-3.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-4.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-4.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 3.7 www.ti.com Terminal Functions The terminal functions tables (Table 3-5 through Table 3-32) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-5. BOOT Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION (3) BOOT ARM Boot Mode configuration bits. These pins are multiplexed between ARM boot mode and the Video Port Interface (VPIF). At reset, the boot mode inputs BTMODE[3:0] are sampled to determine the ARM boot configuration. See below the boot modes set by these inputs. For more details on the types of boot modes, see the Section 4.4.1, Boot Modes.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-6. Oscillator/PLL Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION OSCILLATOR, PLL DEV_MXI/ DEV_CLKIN B15 I DEV_DVDD18 Crystal input DEV_MXI for DEV oscillator (system oscillator, between 27 MHz and 35 MHz, typically 33 MHz or 33.3 MHz). If the internal oscillator is bypassed, this pin is the 1.8-V external oscillator clock input. DEV_MXO A15 O DEV_DVDD18 Crystal output for DEV oscillator.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-7. Clock Generator Terminal Functions SIGNAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. CLKOUT0 C13 O/Z DVDD33 Configurable output clock. GP[3]/ AUDIO_CLK0 AB3 I/O/Z IPD DVDD33 This pin is multiplexed between GPIO and the Audio Clock Selector. For the audio clock selector, this pin is the configurable AUDIO_CLK0 output.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION EMIFA BOOT CONFIGURATION VP_DOUT4/ CS2BW AA7 I/O/Z IPD DVDD33 EMIFA CS2 space data bus width. This pin is multiplexed between EMIFA control and the VPIF. At reset, the input state is sampled to set the EMIFA data bus width for the CS2 (boot) chip select region.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued) SIGNAL NAME NO. PCI_RSV3/DIOR/ GP[19]/EM_WAIT5/ (RDY5/BSY5) E10 PCI_FRAME/ HINT/ EM_BA[0] D6 TYPE (1) I/O/Z I/O/Z OTHER (2) (3) DESCRIPTION IPU DVDD33 This pin is multiplexed between PCI, ATA, GPIO, and EMIFA. For EMIFA, this pin is wait state extension input 5 EM_WAIT5 (I).
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued) SIGNAL OTHER (2) (3) DESCRIPTION NO. PCI_AD24/ DD8/ HD24/EM_A[8] D8 I/O/Z IPD DVDD33 This pin is multiplexed between PCI, ATA, HPI, and EMIFA. For EMIFA, this pin is address bit 8 output EM_A[8] (O/Z). This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) NAME NO.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued) SIGNAL 38 TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. PCI_STOP/ HCNTL0/ EM_WE D5 I/O/Z IPU DVDD33 This pin is multiplexed between PCI, HPI, and EMIFA. In EMIFA mode, this pin is the write enable output EM_WE (O/Z). PCI_CBE2/ HDS2/ EM_CS2 C4 I/O/Z IPU DVDD33 This pin is multiplexed between PCI, HPI, and EMIFA.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-10. DDR2 Memory Controller Terminal Functions SIGNAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-10. DDR2 Memory Controller Terminal Functions (continued) SIGNAL NAME NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-11. Peripheral Component Interconnect (PCI) Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION PCI Notes: When PCI boot mode is not used, for proper device operation out of reset PCIEN must be "0". The PCI pin functions are enabled when PCIEN = 1 (PCI mode). This can be done via an external PU on the PCIEN pin (AC6) or by setting the PCIEN bit (bit 2) in the PINMUX0 register to a "1" after device reset.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-11. Peripheral Component Interconnect (PCI) Terminal Functions (continued) SIGNAL 42 NAME NO. PCI_CBE0 / ATA_CS0/ GP[33]/EM_A[18] F4 Device Overview TYPE (1) I/O/Z OTHER (2) [IPU] DVDD33 (3) DESCRIPTION This pin is multiplexed between PCI, ATA, GPIO, and EMIFA. In PCI mode, this pin is the PCI command/byte enable 0 PCI_CBE0 (I/O/Z).
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-11. Peripheral Component Interconnect (PCI) Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) NAME NO.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-11. Peripheral Component Interconnect (PCI) Terminal Functions (continued) SIGNAL (1) 44 TYPE (1) OTHER (2) NAME NO. PCI_AD7/ HD7/EM_D7 E2 I/O/Z [IPD] DVDD33 PCI_AD6/ HD6/EM_D6 F3 I/O/Z [IPD] DVDD33 PCI_AD5/ HD5/EM_D5 E1 I/O/Z [IPD] DVDD33 PCI_AD4/ HD4/EM_D4 G5 I/O/Z [IPD] DVDD33 (3) DESCRIPTION These pins are multiplexed between PCI, HPI, and EMIFA.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-12. EMAC [G]MII and MDIO Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION EMAC [G]MII RFTCLK H1 I IPD DVDD33 GMTCLK P2 O/Z DVDD33 GMII source asynchronous transmit clock MTCLK R1 I IPD DVDD33 [G]MII transmit clock input MTXD7 P1 MTXD6 N4 MTXD5 N3 MTXD4 N2 MTXD3 N1 O/Z DVDD33 [G]MII transmit data [7:0]. For 1000 GMII operation, MTXD[7:0] are used.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-13. VLYNQ Terminal Functions SIGNAL NAME NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-14. HPI Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION Host-Port Interface (HPI) HPI is enabled by the PINMUX0.HPIEN =1 (and PCIEN = 0 and ATAEN dependent for 16-/32-bit modes). For more detailed information on the HPI pin muxing, see Section 4.7.3.1, PCI, HPI, EMIFA, and ATA Pin Muxing. PCI_PERR/ HCS / EM_DQM1 C3 I/O/Z IPU DVDD33 This pin is multiplexed between PCI, HPI, and EMIFA.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-14. HPI Terminal Functions (continued) SIGNAL NAME NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-14. HPI Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. PCI_IRDY/ HRDY / EM_A[17]/(CLE) A3 I/O/Z IPU DVDD33 This pin is multiplexed between PCI, HPI, and EMIFA. In HPI mode, this pin is the HPI host ready output from DSP to host, HRDY (O/Z). PCI_FRAME/ HINT /EM_BA[0] D6 I/O/Z IPU DVDD33 This pin is multiplexed between PCI, HPI, and EMIFA.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-15. USB Terminal Functions SIGNAL TYPE (1) OTHER (2) (3) DESCRIPTION (4) NAME NO. USB_DP A19 A I/O USB_DN A20 A I/O USB_R1 D18 A I/O (4) USB_DRVVBUS/ GP[22] B18 I/O/Z IPD DVDD33 USB_VSSREF C18 GND (4) USB_VDDA3P3 F18 S (4) USB_VDD1P8 E18 S (4) S (4) USB 2.0 USB_VDDA1P2LDO (1) (2) (3) (4) 50 E17 USB bidirectional Data Differential signal pair [positive/negative].
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-16. Video-Port Interface (VPIF) Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION VIDEO-PORT INTERFACE (VPIF) – CAPTURE VP_CLKIN0 AC13 I IPD DVDD33 VPIF capture channel 0 input clock (I). VP_CLKIN1 AB18 I IPD DVDD33 VPIF capture channel 1 input clock (I). VP_DIN15_VP_VSYNC/ TS0_DIN7 AC18 I IPD DVDD33 This pin is multiplexed between the VPIF and TSIF0.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-16. Video-Port Interface (VPIF) Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) NAME NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-17. Transport Stream Interface 0 (TSIF0) Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION TSIF0 PARALLEL INPUT (PINMUX0.PTSIMUX = 10) TS0_CLKIN UCTS1/USD1/ TS0_EN_WAITO/ GP[26] AC19 Y17 I IPD DVDD33 TSIF0 receive clock input (I). I/O/Z IPU DVDD33 This pin is multiplexed between UART1, TSIF0, and GPIO. When TSIF0 input is enabled (PINMUX0.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-17. Transport Stream Interface 0 (TSIF0) Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION TSIF0 PARALLEL OUTPUT (PINMUX0.PTSIMUX = 10) VP_CLKO3/ TS0_CLKO AC10 O/Z DVDD33 This pin is multiplexed between the VPIF and TSIF0. When TSIF0 output is enabled (PINMUX0.PTSOMUX = 1x), this pin is the transmit clock output, TS0_CLKO (O/Z).
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-18. Transport Stream Interface 1 (TSIF1) Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION TSIF1 INPUT – UART0 MUXING (PINMUX0.TSSIMUX = 01) TS1_CLKIN AC11 I IPD DVDD33 TSIF1 receive clock input (I). URXD0/ TS1_DIN AB13 I IPD DVDD33 This pin is multiplexed between UART0 and TSIF1. When TSIF1 input on UART0 muxing is enabled (PINMUX0.TSSIMUX = 01), this pin is the serial data input, TS1_DIN (I).
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-18. Transport Stream Interface 1 (TSIF1) Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION TSIF1 OUTPUT – VPIF DOUT MUXING (PINMUX0.TSSOMUX = 10) VP_CLKIN3/ TS1_CLKO AC9 I/O/Z IPD DVDD33 This pin is multiplexed between the VPIF and TSIF1. When TSIF1 output is enabled (PINMUX0.TSSOMUX = 1x), in synchronous/asynchronous modes, this pin is the transmit clock output, TS1_CLKO (O/Z).
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-19. I2C Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION I2C (1) (2) SCL U5 I/O/Z SDA U4 I/O/Z DVDD33 I2C clock output SCL. For proper device operation, this pin must be pulled up via external resistor. DVDD33 I2C bidirectional data signal SDA. For proper device operation, this pin must be pulled up via external resistor.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-21. Multichannel Audio Serial Port (McASP) Terminal Functions SIGNAL NAME NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-22. Clock Recovery Generator (CRGEN) Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION CRGEN1 ONLY MODE (PINMUX0.CRGMUX = 001) URXD2/ CRG1_VCXI/ GP[39]/ CRG0_VCXI AB20 I/O/Z IPD DVDD33 This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0. When CRGEN1 is enabled (PINMUX0.CRGMUX = 001), this pin is CRGEN1 input clock from external VCXO, CRG1_VCXI (I).
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-23. UART0 Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION Actual UART0 pin functions are determined by the PINMUX0 and PINMUX1 register bit settings. For more details, see Section 4.7.3, Pin Multiplexing. UART0 WITH MODEM CONTROL (PINMUX1.UART0CTL = 00) URXD0/ TS1_DIN UTXD0/ URCTX0/ TS1_PSTIN AB13 Y13 I IPD DVDD33 This pin is multiplexed between UART0 and TSIF1.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-23. UART0 Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION UART0 IrDA/CIR FUNCTION (PINMUX1.UART0CTL = 1x) URXD0/ TS1_DIN AB13 I IPD DVDD33 This pin is multiplexed between UART0 and TSIF1. When TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this pin is UART0 IrDA/CIR receive data, URXD0 (I).
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-24. UART1 Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION UART1 WITH FLOW CONTROL (PINMUX1.UART1CTL = 00) Actual UART1 pin functions are determined by the PINMUX0 and PINMUX1 register bit settings. For more details, see Section 4.7.3, Pin Multiplexing. URXD1/ TS0_DIN7/ GP[23] UTXD1/ URCTX1/ TS0_DOUT7/ GP[24] Y18 AB19 I/O/Z IPD DVDD33 This pin is multiplexed between UART1, TSIF0, and GPIO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-25. UART2 Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION UART2 WITH FLOW CONTROL (PINMUX1.UART2CTL = 00) Actual UART2 pin functions are determined by the PINMUX0 and PINMUX1 register bit settings. For more details, see Section 4.7.3, Pin Multiplexing. URXD2/ CRG1_VCXI/ GP[39]/ CRG0_VCXI I/O/Z IPD DVDD33 This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-26. PWM Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) DESCRIPTION – DVDD33 This pin is multiplexed between PWM0, CRGEN0, and TSIF1. When not overridden by CRGEN or TSIF1 output muxing (PINMUX0.CRGMUX ≠ 10x and PINMUX0.TSSOMUX ≠ 11), this pin is the pulse width modulation 0 output, PWM0 (O/Z). – DVDD33 This pin is multiplexed between PWM1 and TSIF1. When not overridden by TSIF1 output muxing (PINMUX0.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-27. Timer 0, Timer 1, and Timer 2 Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION Timer 0 TINP0L Y7 I/O/Z IPD DVDD33 Timer0 lower input. This pin is the Timer0 input for 64-mode operation. For 32-bit timer operation, this pin is the input for the Timer0 lower 32-bit counter. TINP0U AA6 I/O/Z IPD DVDD33 Timer0 upper input.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-28. ATA Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION ATA ATA is enabled by the PINMUX0.ATAEN =1 (and PCIEN = 0). For more detailed information on the ATA pin muxing, see Section 4.7.3.1, PCI, HPI, EMIFA, and ATA Pin Muxing. PCI_CBE0/ ATA_CS0 / GP[33]/EM_A[18] F4 I/O/Z IPU DVDD33 This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-28. ATA Terminal Functions (continued) SIGNAL NAME NO.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-29. General Purpose Input/Output (GPIO) Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER (2) (3) DESCRIPTION GPIO The DM6467T device does not support GP[47:43], GP[35:34], GP[31:27], GP[15:14], and GP[9] signals (not pinned out). GP[7:0] pins have dedicated ARM926 and DSP interrupts. When PCI is used, GP[19:16] pins are reserved. GP[0] W5 I/O/Z IPD DVDD33 GP[0] (I/O/Z). This pin is general-purpose input/output 0.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-29. General Purpose Input/Output (GPIO) Terminal Functions (continued) SIGNAL TYPE (1) OTHER (2) (3) DESCRIPTION NAME NO. PCI_RSV4/ DIOW/ GP[20]/ EM_WAIT4 A11 PCI_RSV5/ IORDY/ GP[21]/ EM_WAIT3 D11 I/O/Z IPU DVDD33 USB_DRVVBUS/ GP[22] B18 I/O/Z IPD DVDD33 This pin is multiplexed between USB and GPIO. When not used for USB (PINMUX0.VBUSDIS = 1), this pin is GP[22] (I/O/Z).
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-29. General Purpose Input/Output (GPIO) Terminal Functions (continued) SIGNAL 70 NAME NO. GP[43:47] n/a Device Overview TYPE (1) – OTHER (2) – (3) DESCRIPTION GP[43:47] are not pinned out on this device.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-30. Reserved Terminal Functions SIGNAL TYPE (1) OTHER DESCRIPTION NAME NO. RSV1 A1 Reserved. For proper device operation, this pin must be tied directly to VSS. RSV2 A2 Reserved. For proper device operation, this pin must be tied directly to VSS. RSV3 A22 Reserved. For proper device operation, this pin must be tied directly to VSS. RSV4 A23 Reserved. (Leave unconnected, do not connect to power or ground.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-31. Supply Terminal Functions SIGNAL NAME NO. TYPE (1) OTHER DESCRIPTION SUPPLY VOLTAGE PINS B7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G7 H6 J6 K6 K7 DVDD33 M3 S 3.3-V I/O supply voltage (see the Power-Supply Decoupling section of this data manual) S 1.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-31. Supply Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) OTHER DESCRIPTION R18 T18 DVDDR2 T19 U19 S 1.8-V DDR2 I/O supply voltage (see the Power-Supply Decoupling section of this data manual) S 1.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-31. Supply Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) OTHER DESCRIPTION R8 R9 R10 R11 R13 R14 R15 T8 T9 T10 T11 T13 T14 T15 CVDD U8 S 1.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-32. Ground Terminal Functions SIGNAL NAME NO.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 3-32. Ground Terminal Functions (continued) SIGNAL NAME NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 3-32. Ground Terminal Functions (continued) SIGNAL NAME NO.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 3.8 3.8.1 www.ti.com Device Support Development Support TI offers an extensive line of development tools for the TMS320DM646x DMSoC platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE).
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, CUT), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz or gigahertz (for example, "1" is the default [1-GHz DSP, 500-MHz ARM9, 150-MHz VPIF, 400-MHz DDR2]).
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 3.9 3.9.1 www.ti.com Documentation Support Related Documentation From Texas Instruments The following documents describe the TMS320DM646x Digital Media System-on-Chip (DMSoC). Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 4 Device Configurations 4.1 System Module Registers The system module includes status and control registers for configuration of the device.Brief descriptions of the various registers are shown in Table 4-1. System Module registers required for device configurations are discussed in the following sections. Table 4-1.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 4-1. System Module Register Memory Map (continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C4 0078 ARMINTCLR DSP to ARM Interrupt Clear (see Section 4.7.3.11, ARM/DSP Communications Interrupts). 0x01C4 007C ARMWAIT ARM Memory Wait State Control (see Section 4.4.2.5, ARMWAIT Register).
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TMS320DM6467T www.ti.com 4.2 SPRS605C – JULY 2009 – REVISED JUNE 2012 Power Considerations The DM6467T provides several means of managing power consumption. As described in the Section 7.3.4, DM6467T Power and Clock Domains, the DM6467T has one single power domain—the “Always On” power domain. Within this power domain, the DM6467T utilizes local clock gating via the Power and Sleep Controller (PSC) to achieve power savings. For more details on the PSC, see Section 7.3.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 4-2. VDD3P3V_PWDN Register Bit Descriptions BIT NAME 31:29 RESERVED 28 USBV 27 CLKOUT 26 RSV Reserved. Read returns "0". 25 SPI SPI Powerdown Control. This bit controls the six SPI interface pins: SPI_CLK, SPI_EN, SPI_CS0, SPI_CS1, SPI_SOMI, and SPI_SIMO. 24 VLYNQ 23:22 RESERVED 21 GMII 20 MII 19 MCASP1 McASP1 Powerdown Control. This bit controls the three McASP1 pins: ACLKX1, AHCLKX1, and AXR1[0].
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 4-2. VDD3P3V_PWDN Register Bit Descriptions (continued) BIT NAME DESCRIPTION UART2 Data Powerdown Control. This bit controls the URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI and UTXD2/URCTX2/CRG1_PO/GP[40]/CRG0_PO pins. 8 UR2DAT 7 UR1FC 6 UR1DAT UART1 Data Powerdown Control. This bit controls the URXD1/TS0_DIN7/GP[23] and UTXD1/URCTX1/TS0_DOUT7/GP[24] pins. 5 UR0MDM UART0 Modem Control Powerdown Control.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 4.3 www.ti.com Clock Considerations Global device and local peripheral clocks are controlled by the PLL Controllers (PLLC1 and PLLC2) and the Power and Sleep Controller (PSC). In addition, the System Module Video Clock Control (VIDCLKCTL), TSIF Control (TSIFCTL), and Clock and Oscillator Control (CLKCTL) registers configure the clock sources to the VPIF, TSIF, CRGEN peripherals, and the Auxiliary Oscillator.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 4-3. DM6467T Default Module States LPSC # 0 ARM Enable DSP C64x+ If DSPBOOT = 0 then, Enable and Module Local Reset is asserted (MDSTATn.LRST = 0). If DSPBOOT = 1 then, Enable and Module Local Reset is asserted (MDSTATn.LRST = 1). 2 HDVICP0 SwRstDisable 3 HDVICP1 SwRstDisable 4 EDMACC SwRstDisable 5 EDMATC0 SwRstDisable 6 EDMATC1 SwRstDisable 7 EDMATC2 SwRstDisable 8 EDMATC3 SwRstDisable 1 9 USB2.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 4.3.2 www.ti.com Clock Control This section describes the following registers: the VPIF (Video)/TSIF clock control and clock disable registers and the Clock and Oscillator control register. 4.3.2.1 Video Clock Control Register The Video Clock Control (VIDCLKCTL) register allows the user to select/control the clock muxing for the video channels' (i.e., channels 1, 2, and 3) output clock source.
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TMS320DM6467T www.ti.com 4.3.2.2 SPRS605C – JULY 2009 – REVISED JUNE 2012 TSIF Control The TSIF Control (TSIFCTL) registers allows the user to select/control the clock muxing for the counter and serial output of TSIF1 andthe counter and parallel/serial output for TSIF0.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 4.3.2.3 www.ti.com Video and TSIF Clock Disable The Video Source Clock Disable (VSCLKDIS) register allows the user to disable the selected Video (VPIF), TSIF, and CRGEN module input clocks. Note: To ensure glitch-free operation, the clock should be disabled before changing the clock source frequency or muxing via the VIDCLKCTL and TSIFCTL.
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TMS320DM6467T www.ti.com 4.3.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 4-7. CLKCTL Register Bit Descriptions (continued) 92 BIT NAME 11:8 AUD_CLK1 AUDIO_CLK1 Source. This field selects the clock source for the AUDIO_CLK1 output.
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TMS320DM6467T www.ti.com 4.4 SPRS605C – JULY 2009 – REVISED JUNE 2012 Boot Sequence The boot sequence is a process by which the device's memory is loaded with program and data sections, and by which some of the device's internal registers are programmed with predetermined values. The boot sequence is started automatically after each device-level global reset. For more details on device-level global resets, see Section 7.7, Reset.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 4.4.2.2 www.ti.com BOOTSTAT Register The Boot Status (BOOTSTAT) register indicates the status of the device boot process (e.g., boot error, boot complete, or watchdog timer reset). 31 30 20 19 16 WDRST RESERVED BOOTERR R/W-0 R-000 0000 0000 R-0000 15 1 0 RESERVED BC R-0000 0000 0000 000 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-7. BOOTSTAT Register Table 4-9.
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TMS320DM6467T www.ti.com 4.4.2.3 SPRS605C – JULY 2009 – REVISED JUNE 2012 BOOTCFG Register The Boot Configuration (BOOTCFG) register is a read-only register that indicates the value of the device bootmode and configuration pins latched at the end of reset. During a hard reset (POR or RESET pin active [low]), the values of the CFG pins (i.e., BTMODE[3:0], CS2BW, PCIEN, DSPBOOT) are propagated through the BOOTCFG register to the Boot Controller.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 4-10. BOOTCFG Register Bit Descriptions BIT NAME 31:18 RESERVED 17 DSP_BT 16 PCIEN 15:9 RESERVED 8 CS2_BW 7:4 RESERVED 3:0 BOOTMODE DESCRIPTION Reserved. Read returns "0". DSP Boot. Latched from DSPBOOT input at the rising edge of RESET or POR. 0 = ARM boots C64x+. 1 = C64x+ self-boots. This bit will cause the DSP to be released from reset automatically.
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TMS320DM6467T www.ti.com 4.4.2.4 SPRS605C – JULY 2009 – REVISED JUNE 2012 ARMBOOT Register The ARM Boot Configuration (ARMBOOT) register is used to control the ARM926 boot. The ARMBOOT value does not change as a result of a soft reset, instead the last value written is retained. When ROM boot is selected (BTMODE[3:0] ≠ 0100), a jump to the internal TCM ROM (0x0000 8000) is forced into the first fetched instruction word.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 4-12. ARMWAIT Register Bit Descriptions 98 BIT NAME 31:1 RESERVED 0 RAMWAIT Device Configurations DESCRIPTION Reserved. Read returns "0". ARM TCM RAM Wait State Configuration. 0 = TCM RAM wait state disabled. 1 = TCM RAM wait state enabled.
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TMS320DM6467T www.ti.com 4.5 SPRS605C – JULY 2009 – REVISED JUNE 2012 Configurations At Reset Some device configurations are determined at reset. The following subsections give more details. 4.5.1 Device and Peripheral Configurations at Device Reset Table 3-5, BOOT Terminal Functions lists the device boot and configuration pins that are latched at device reset for configuring basic device settings for proper device operation.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 4-13. Default Functions Affected by Device Boot and Configuration Pins (continued) DEVICE BOOT AND CONFIGURATION PINS DSPBOOT BOOT SELECTED Bit = 0, DSP is booted by the ARM Bit =1, DSP boots self from EMIFA PIN MUX CONTROL – GLOBAL SETTING – PERIPHERAL SETTING Note: that either NOR Flash or ROM must be connected to the first EMIFA chip select space (CS2). The EMIFA does not support direct execution from NAND Flash.
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TMS320DM6467T www.ti.com 4.5.4 SPRS605C – JULY 2009 – REVISED JUNE 2012 DSPBOOT The DSPBOOT input determines DSP operation at reset. For most applications, the ARM is the master device and controls the reset and boot of the DSP. Under this scenario (DSPBOOT = 0), the DSP will remain disabled (held in reset) after reset. The ARM is responsible for releasing DSP from reset.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 4.6 www.ti.com Configurations After Reset The following sections provide details on configuring the device after reset. Multiplexed pin are configured both at and after reset. Section 4.5.1, Device and Peripheral Configurations at Device Reset, discusses multiplexed pin control at reset. For more details on multiplexed pins control after reset, see Section 4.7, Multiplexed Pin Configurations. 4.6.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 31 23 15 14 22 20 19 18 16 RESERVED HDVICP1P(1) RSV HDVICP0P(1) R-0000 0000 0 R/W-011 R-0 R/W-011 12 11 8 7 6 4 3 2 0 RSV DSPDMAP RSV DSPCFGP (1) RSV ARMDATAP RSV ARMINSTP R-0 R/W-100 R-0 R/W-100 R-0 R/W-100 R-0 R/W-100 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-11.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 31 30 28 27 www.ti.com 26 24 23 22 20 19 18 16 RSV VDCEP RSV PCIP RSV HPIP RSV VLYNQP R-0 R/W-100 R-0 R/W-110 R-0 R/W-110 R-0 R/W-101 15 14 12 11 10 8 7 3 2 0 RSV ATAP RSV USBP RESERVED EMACP R-0 R/W-101 R-0 R/W-101 R-0000 0 R/W-101 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-12. MSTPRI1 Register [0x01C4 0040] Table 4-16.
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TMS320DM6467T www.ti.com 31 SPRS605C – JULY 2009 – REVISED JUNE 2012 30 28 27 26 24 23 22 20 19 18 16 RSV TSIF1P RSV TSIF0P RSV VP1P RSV VP0P R-0 R/W-001 R-0 R/W-001 R-0 R/W-001 R-0 R/W-001 15 14 12 11 10 8 7 6 4 3 2 0 RSV EDMATC3P RSV EDMATC2P RSV EDMATC1P RSV EDMATC0P R-0 R/W-010 R-0 R/W-010 R-0 R/W-010 R-0 R/W-010 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-13. MSTPRI2 Register Table 4-17.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 4.6.2.1 www.ti.com HPICTL Register The HPI control register (HPICTL) [0x01C4 0030] controls write access to HPI control and address registers and determines the host time-out value. HPICTL is not reset by a soft reset so that the HPI width will remain correctly configured. Figure 4-14 and Table 4-18 describe in detail the HPICTL register.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 4-19. USBCTL Register Bit Descriptions BIT NAME 31:19 RESERVED DESCRIPTION 18 DATAPOL USB Data Polarity. 0 = Inverted data. 1 = Normal data polarity [default]. 17 VBUSVAL VBUS Sense Control. 0 = Disabled [default]. 1 = Session starts. 16 USBID 15:9 RESERVED Reserved. Read returns "0". 8 PHYCLKGD USB PHY Power and Clock Good. 0 = PHY power is not ramped or PLL is not locked [default].
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 4.6.2.3 www.ti.com PWMCTL (Trigger Source) Control Register The PWM control register (PWMCTL) [0x01C4 0054] chip-level connections of both PWM0 and PWM1. Figure 4-16 and Table 4-20 describe in detail the PWMCTL register. 31 16 RESERVED R-0000 0000 0000 0000 15 8 7 4 RESERVED PWM11TRG R-0000 0000 R/W-1111 3 0 PWM0TRG R/W-1111 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-16.
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TMS320DM6467T www.ti.com 4.6.2.4 SPRS605C – JULY 2009 – REVISED JUNE 2012 EDMATCCFG Register The EDMA Transfer Controller Default Burst Size Configuration Register (EDMATCCFG) [0x01C4 0058] configures the default burst size (DBS) for EDMA TC0, EDMA TC1, EDMA TC2, and EDMA TC3. Figure 4-17 and Table 4-21 describe in detail the EDMATCCFG register.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 4.7 www.ti.com Multiplexed Pin Configurations DM6467T makes extensive use of pin multiplexing to accommodate a large number of peripheral function in the smallest possible package, providing the ultimate flexibility for end applications. The Pin Multiplex Registers PINMUX0 and PINMUX1 in the System Module are responsiblie for controlling all pin multiplexing functions on the DM6467T.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 4-22. PINMUX0 Register Bit Descriptions BIT DESCRIPTION 31 VBUSDIS This bit disables USB_DRVVBUS output. 0 = USB_DRVVBUS function selected. 1 = GP[22] function selected. 30 STCCK This bit enables STC Source Clock input. 0 = GP[4] function selected. 1 = STC_CLKIN function selected. 29 AUDCK1 This bit enables AUDIO_CLK1 output. 0 = GP[2] function selected. 1 = AUDIO_CLK1 function selected.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 4.7.2.2 www.ti.com PINMUX1 Register Description The Pin Multiplexing 1 Register controls the pin function in the UART0, UART1, and UART2 Blocks. The PINMUX1 register format is shown in Figure 4-19 and the bit field descriptions are given in Table 4-23. Some muxed pins are controlled by more than one PINMUX bit field. For the combination of the PINMUX bit fields that control each muxed pin, see Section 4.7.3, Pin Multiplexing Details.
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TMS320DM6467T www.ti.com 4.7.3 SPRS605C – JULY 2009 – REVISED JUNE 2012 Pin Multiplexing Details This section discusses how to program each Pin Mux Register to select the desired peripheral functions and pin muxing. See the individual pin mux sections for pin muxing details for a specific muxed pin. For details on PINMUX0 and PINMUX1 registers, see Section 4.7.2, Pin Muxing Selection After Reset. 4.7.3.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 4-25.
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TMS320DM6467T www.ti.com 4.7.3.2 SPRS605C – JULY 2009 – REVISED JUNE 2012 PWM Signal Muxing The two PWM outputs will be configured as PWM pin functions by default. The PWM functions may be overridden by the settings of various PINMUX0 bit fields as shown in Table 4-26 and Table 4-27. Table 4-26. PWM0 Pin Muxing PIN FUNCTION CRGMUX ≠ 10x TSSOMUX ≠ 11 CRGMUX = 10x TSSOMUX ≠ 11 TSSOMUX = 11 PWM0 CRG0_PO TS1_ENAO Table 4-27.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 4.7.3.3 www.ti.com TSIF0 Input Signal Muxing (Serial/Parallel) The TSIF 0 (TS0) input signals have muxing options for both parallel or serial operation as configured by the TPSIMUX bits as shown in Table 4-28. Table 4-28.
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TMS320DM6467T www.ti.com 4.7.3.4 SPRS605C – JULY 2009 – REVISED JUNE 2012 TSIF0 Output Signal Muxing (Serial/Parallel) The TSIF 0 (TS0) output signals have muxing options for both parallel or serial operation as configured by the TPSOMUX bits as shown in Table 4-29. Table 4-29.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 4.7.3.5 www.ti.com TSIF1 Input Signal Muxing (Serial Only) The TSIF 1 (TS1) input signals have three muxing options as configured by the TSSIMUX bits as shown in Table 4-30. When TSSIMUX = 11, the TSSI data and control pins are muxed onto the VP_DIN[7:4] regardless of the value of TSPOMUX. Table 4-30.
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TMS320DM6467T www.ti.com 4.7.3.6 SPRS605C – JULY 2009 – REVISED JUNE 2012 TSIF1 Output Signal Muxing (Serial Only) The TSIF 1 (TS1) output signals are muxed with either the VP_DOUT signals or UART0, UART2, and PWM signals as selected by TSSOMUX (PINMUX0 register). The TS1 output pin muxing is shown in Table 4-31. Table 4-31.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 4.7.3.7 www.ti.com CRGEN Signal Muxing The two CRGEN modules share pins with UART2 and PWM0. The CRGEN function is selected using the CRGMUX bit field in the PINMUX0 register (see Table 4-32). Table 4-32.
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TMS320DM6467T www.ti.com 4.7.3.8 SPRS605C – JULY 2009 – REVISED JUNE 2012 UART0 Pin Muxing The UART0 module can operate as either a UART or IrDA/CIR interface. The UART0 pin muxing is controlled by the UART0CTL bit field in the PINMUX1 register and the TSPOMUX, TSSIMUX, and TSSOMUX bit fields in the PINMUX0 register. Muxing options are shown in Table 4-33 and Table 4-34.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 4-34.
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TMS320DM6467T www.ti.com 4.7.3.9 SPRS605C – JULY 2009 – REVISED JUNE 2012 UART1 Pin Muxing The UART1 module can operate as either a UART or IrDA/CIR interface. The UART1 pin muxing options are shown in Table 4-35. When UART operation is selected, UART1CTL must be set to either ‘00’ for UART with flow control or ‘01’ for UART without flow control signals. When IrDA/CIR operation is selected, UART1CTL must be set to ‘10’ to use the IrDA/CIR signals.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 4.7.3.10 UART2 Pin Muxing The UART2 module can operate as either a UART or IrDA/CIR interface. The UART2 pin muxing options are shown in Table 4-36 through Table 4-38. When UART operation is selected, UART2CTL must be set to either ‘00’ for UART with flow control or ‘01’ for UART without flow control signals. When IrDA/CIR operation is selected, UART2CTL must be set to ‘10’ to use the IrDA/CIR signals.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 4-37. UART2 Ready-to-Send ( URTS2 ) Pin Muxing PIN FUNCTION URTS2 / UIRTX2/ TS0_PSTIN/ GP[41] TSPIMUX[1] TSPIMUX[0] UART2CTL[1] UART2CTL[0] 0 x 0 0 0 x 0 1 GP[41] 0 x 1 0 UIRTX2 0 x 1 1 GP[41] 1 x x x TS0_PSTIN URTS2 Table 4-38.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 4.7.3.11 ARM/DSP Communications Interrupts The system module includes registers for generating interrupts between the ARM and DSP. The DSPINT register shows the status of the ARM-to-DSP interrupts. The DSPINT register format is shown in Figure 4-20. Table 4-39 describes the register bit fields.
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TMS320DM6467T www.ti.com 31 SPRS605C – JULY 2009 – REVISED JUNE 2012 30 29 28 27 26 25 24 23 22 21 20 5 4 19 18 17 16 Reserved R-0000 0000 0000 0000 15 14 13 3 2 1 0 Reserved 12 11 10 9 INTNMI 8 7 6 Reserved INTDSP3 INTDSP2 INTDSP1 INTDSP0 R-0000 000 R/W-0 R-0000 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R = Read, W = Write, n = Value at reset Figure 4-21. DSPINTSET Register [0x01C4 0064] Table 4-40.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 31 30 29 28 www.ti.com 27 26 25 24 23 22 21 20 19 18 17 5 4 3 2 1 16 Reserved R-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 0 Reserved INTARM0 R-0000 0000 0000 000 R-0 LEGEND: R = Read only, n = Value at reset Figure 4-23. ARMINT Status Register [0x01C4 0070] Table 4-42. ARMINT Status Register Bit Descriptions (1) (1) BIT NAME 31:1 Reserved Reserved. A read returns 0.
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TMS320DM6467T www.ti.com 31 SPRS605C – JULY 2009 – REVISED JUNE 2012 30 29 28 27 26 25 24 23 22 21 20 19 18 17 5 4 3 2 1 16 Reserved R-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 0 Reserved INTARM0 R-0000 0000 0000 000 R/W-0 LEGEND: R = Read, W = Write, n = Value at reset Figure 4-25. ARMINTCLR Register [0x01C4 0078] Table 4-44. ARMINTCLR Register Bit Descriptions (1) BIT NAME 31:1 Reserved Reserved. A read returns 0.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 4.7.3.12 Emulation Control The flexibility of the DM646xT DMSoC architecture allows either the ARM or DSP to control the various peripherals (setup registers, service interrupts, etc.). While this assignment is purely a matter of software convention, during an emulation halt it is necessary for the device to know which peripherals are associated with the halting processor so that only those modules receive the suspend signal.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 4-45. SUSPSRC Register Bit Descriptions (continued) BIT NAME DESCRIPTION 20 UART1SRC UART1 Emulation Suspend Source. 0 = ARM emulation suspend. 1 = DSP emulation suspend. 19 UART0SRC UART0 Emulation Suspend Source. 0 = ARM emulation suspend. 1 = DSP emulation suspend. 18 I2CSRC 17 MCASP1SRC McASP1 Emulation Suspend Source. 0 = ARM emulation suspend. 1 = DSP emulation suspend.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 4.8 4.8.1 www.ti.com Debugging Considerations Pullup/Pulldown Resistors Proper board design should ensure that input pins to the TMS320DM646x DMSoC device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The TMS320DM646x DMSoC features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal functions table.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 5 System Interconnect On the DM6467T device, the C64x+ megamodule, the ARM subsystem, the EDMA3 transfer controllers, and the system peripherals are interconnected through a switch fabric architecture. The switch fabric is composed of multiple switched central resources (SCRs) and multiple bridges.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 6 Device Operating Conditions 6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) (1) Supply voltage ranges: Input and Output voltage ranges: Core (CVDD, DEV_CVDD, AUX_CVDD) (2) –0.5 V to 1.5 V I/O, 3.3V (DVDD33, USB_VDDA3P3) (2) -0.3 V to 3.8 V I/O, 1.8V (DVDDR2, PLL1VDD18, PLL2VDD18, DEV_DVDD18, AUX_DVDD18, USB_VDD1P8) (2) -0.3 V to 2.6 V V I/O, 3.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 6.2 www.ti.com Recommended Operating Conditions Supply voltage, Core (CVDD, DEV_CVDD, AUX_CVDD) (1) CVDD (-1G) Supply voltage, I/O, 3.3V (DVDD33, USB_VDDA3P3) DVDD Supply voltage, I/O, 1.8V (DVDDR2, PLL1VDD18, PLL2VDD18, DEV_DVDD18, AUX_DVDD18, USB_VDD1P8 (2)) Supply ground (VSS, PLL1VSS, PLL2VSS, DEV_VSS AUX_VSS (3), USB_VSSREF) VSS MIN NOM MAX UNIT 1.235 1.3 1.365 V 3.14 3.3 3.46 V 1.71 1.8 1.89 V 0 0 0 V 0.49DVDDR2 0.
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TMS320DM6467T www.ti.com 6.3 SPRS605C – JULY 2009 – REVISED JUNE 2012 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) PARAMETER VOH VOL VLDO TEST CONDITIONS (1) MIN TYP 2.8 USB_VDDA3P3 High speed: USB_DN and USB_DP 360 440 High-level output voltage (3.3V I/O except PCI-capable and I2C pins) DVDD33 = MIN, IOH = MAX High-level output voltage (3.3V I/O PCIcapable pins) IOH = –0.5 mA, DVDD33 = 3.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted) (continued) PARAMETER TEST CONDITIONS (1) MIN MAX UNIT IDDD CI Input capacitance 4 pF Co Output capacitance 4 pF 138 Device Operating Conditions DVDD = 1.8 V, DSP clock = 1 GHz ARM Clock = 500 MHz, DDR Clock = 400 MHz TYP 1.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7 Peripheral Information and Electrical Specifications 7.1 Parameter Information Tester Pin Electronics 42 Ω 3.5 nH Transmission Line Z0 = 50 Ω (see Note) 4.0 pF 1.85 pF Data Sheet Timing Reference Point Output Under Test Device Pin (see Note) NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 7.1.3 www.ti.com Timing Parameters and Board Routing Analysis The timing parameter values specified in this data manual do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly.
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TMS320DM6467T www.ti.com 7.3 SPRS605C – JULY 2009 – REVISED JUNE 2012 Power Supplies For more information regarding TI's power management products and suggested devices to power TI DSPs, visit www.ti.com/processorpower. 7.3.1 Power-Supply Sequencing The DM6467T includes one core supply (CVDD), and two I/O supplies—DVDD33 and DVDDR2. To ensure proper device operation, a specific power-up sequence must be followed.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com The DM6467T architecture is divided into the power and clock domains shown in Table 7-1. Table 7-2 further discusses the clock domains and their ratios. Figure 7-4 shows the Clock Domain Block Diagram. Table 7-1.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-2. DM6467T Clock Domains SUBSYSTEM DSP Subsystem ARM926 Subsystem, EDMA3, HDVICP, PCI, VDCE, VPIF, TSIFs, DDR2 Mem Ctlr Peripherals (GPIO, Timers, I2C, PWMs, HPI, EMAC, EMIFA, VLYNQ, SPI, ARM INTC, USB2.0, UARTs, McASPs, CRGENs, SYSTEM) ATA TSIF0 DDR2 PHY (2) (3) (4) PLLC1 SYSCLK1 FIXED RATIO vs. SYSCLK1 FREQ 1:1 CLOCK MODES FREQUENCY (MHz) BYPASS MODE [default RATIO] PLL MODE (-1G) (1) 33.30 MHz 999 MHz 16.65 MHz 499.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com PLL Controller 1 DEV_MXI/ DEV_CLKIN (33.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 PLLOUT CLKIN/OSCIN (A) PLLEN PLL 1 PLLDIV1 (/1 Prog) 0 PLL2_SYSCLK1 (DDR2_PHY) PLLM (A) As selected by the PLL2 PLLCTL register Figure 7-6. PLL2 Structure Block Diagram 7.3.5 Power and Sleep Controller (PSC) The Power and Sleep Controller (PSC) controls device power by gating off clocks to individual peripherals/modules. The PSC consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs).
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-4.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-4.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-4.
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TMS320DM6467T www.ti.com 7.4 SPRS605C – JULY 2009 – REVISED JUNE 2012 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins The DM6467T device includes two options to provide an external clock input for both the system and auxiliary oscillators: • Use an on-chip oscillator with external crystal (fundamental parallel resonant mode only, no overtone support). • Use an external 1.8-V LVCMOS-compatible clock input.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-5. Input Requirements for Crystal on the 27 – 35-MHz System Oscillator PARAMETER MIN NOM MAX Start-Up Time (from power up until oscillating at stable frequency) Oscillation Frequency 27 ESR 33 or 33.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-6. Input Requirements for Crystal on the 24-MHz Auxiliary Oscillator (continued) PARAMETER (1) MIN NOM Frequency Stability Parallel Load Capacitance (C1 and C2) [Max] Frequency Tolerance UNIT ±50 ppm 12 – 20 pF ± 50 ppm ±5 ppm Thermal Stability ± 50 ppm Oscillation Mode Fundamental Aging Drive Level (Max) Shunt Capacitance (Max) (1) MAX n/a 0.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 7.4.2 www.ti.com Clock Input Option 2—1.8-V LVCMOS-Compatible Clock Input 7.4.2.1 33.3-MHz System Oscillator Clock Input Option 2—1.8-V LVCMOS-Compatible Clock Input In this option, a 1.8-V LVCMOS-Compatible Clock Input is used as the external clock input to the system oscillator. The external connections are shown in Figure 7-9. The DEV_MXI/DEV_CLKIN pin is connected to the 1.8-V LVCMOS-Compatible clock source.
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TMS320DM6467T www.ti.com 7.5 SPRS605C – JULY 2009 – REVISED JUNE 2012 Clock PLLs There are two independently controlled PLLs on DM6467T. PLL1 generates the frequencies required for the ARM, DSP, HDVICP0/1, EDMA, and peripherals. PLL2 generates the frequencies required for the DDR2 interface. Any input crystal frequency between 27 MHz and 35 MHz can be used for the System Oscillator (DEV_MXI/DEV_CLKIN). The recommended reference clock for both PLLs is the 33-MHz or 33.3-MHz crystal input.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-7. PLL1 and PLL2 Multiplier Ranges -1G PLL MULTIPLIER (PLLM) MIN MAX PLL1 Multiplier x14 x32 PLL2 Multiplier x14 x32 Table 7-8. PLLC1 Clock Frequency Ranges -1G CLOCK SIGNAL NAME MIN MAX UNIT DEV_MXI/DEV_CLKIN (1) 20 35 MHz PLLOUT 400 1000 MHz 1000 MHz SYSCLK1 (PLLDIV1 Domain) (1) DEV_MXI/DEV_CLKIN input clock is used for both PLL Controllers (PLLC1 and PLLC2). Table 7-9.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 For details on the PLL initialization software sequence, see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number SPRUEP9). For more information on the clock domains and their clock ratio restrictions, see Section 7.3.4, DM6467T Power and Clock Domains.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 7.5.2 www.ti.com PLL Controller Register Description(s) A summary of the PLL controller registers is shown in Table 7-11. For more details, see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number SPRUEP9). Table 7-11.
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TMS320DM6467T www.ti.com 7.5.3 SPRS605C – JULY 2009 – REVISED JUNE 2012 Clock PLL Considerations With External Clock Sources If the internal oscillator is bypassed, to minimize the clock jitter a single clean power supply should power both the DM6467T device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see Section 7.5.5, Clock PLL Electrical Data/Timing (Input and Output Clocks).
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com CLKCTL.AUD_CLK0 STC_CLKIN GP[4]/STC_CLKIN AUX_MXI AUX_MXI/AUX_CLKIN VP0_CLKIN3 VP_CLKIN3/TS1_CLKO VP0_CLKIN2 VP_CLKIN2 VP0_CLKIN1 VP_CLKIN1 VP0_CLKIN0 VP_CLKIN0 CRG1_VCXI URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI 11x UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO 10x CRG0_VCXI 1001 1000 0111 0110 PINMUX0.AUDCK0 0101 0100 0011 1 AUDIO_CLK0 0 GP[3] 0010 PINMUX0.
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TMS320DM6467T www.ti.com 7.5.5 SPRS605C – JULY 2009 – REVISED JUNE 2012 Clock PLL Electrical Data/Timing (Input and Output Clocks) Table 7-12. Timing Requirements for DEV_MXI/DEV_CLKIN (1) (2) (3) (4) -1G NO. (1) (2) (3) (4) (see Figure 7-15) MIN NOM 30.03 MAX UNIT 1 tc(DMXI) Cycle time, DEV_MXI/DEV_CLKIN 28.57 50 ns 2 tw(DMXIH) Pulse duration, DEV_MXI/DEV_CLKIN high 0.45C 0.55C ns 3 tw(DMXIL) Pulse duration, DEV_MXI/DEV_CLKIN low 0.45C 0.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-13. Timing Requirements for AUX_MXI/AUX_CLKIN (1) (2) (3) (see Figure 7-16) -1G NO. MIN NOM (4) UNIT 1 tc(AMXI) Cycle time, AUX_MXI/AUX_CLKIN 2 tw(AMXIH) Pulse duration, AUX_MXI/AUX_CLKIN high 0.45C 0.55C ns 3 tw(AMXIL) Pulse duration, AUX_MXI/AUX_CLKIN low 0.45C 0.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-14. Switching Characteristics Over Recommended Operating Conditions for CLKOUT0 (1) (see Figure 7-17) NO. (1) (2) -1G PARAMETER MIN MAX (2) UNIT 1 tc(CLKOUT0) Cycle time, CLKOUT0 6.734 296.296 ns 2 tw(CLKOUT0H) Pulse duration, CLKOUT0 high 0.4P 0.6P ns 3 tw(CLKOUT0L) Pulse duration, CLKOUT0 low 0.4P 0.6P ns 4 tt(CLKOUT0) Transition time, CLKOUT0 0.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 7.6 www.ti.com Enhanced Direct Memory Access (EDMA3) Controller The EDMA controller handles all data transfers between memories and the device slave peripherals on the DM6467T device. These data transfers include cache servicing, non-cacheable memory accesses, user-programmed data transfers, and host accesses.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-15.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-15.
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TMS320DM6467T www.ti.com 7.6.2 SPRS605C – JULY 2009 – REVISED JUNE 2012 EDMA Peripheral Register Description(s) Table 7-16 lists the EDMA registers, their corresponding acronyms, and DM6467T device memory locations. Table 7-16.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-16.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-16.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-16.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-16.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-16.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-16.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-16.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-16.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-16.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-16.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-16.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-16.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-16.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-16.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-16. DM6467T EDMA Registers (continued) HEX ADDRESS RANGE ACRONYM 0x01C1 0FD4 DFMPPRXY3 0x01C1 0FD8 - 0x01C1 0FFF – REGISTER NAME EDMA3 TC3 Destination FIFO Memory Protection Proxy Register 3 Reserved Table 7-17 shows an abbreviation of the set of registers which make up the parameter set for each of 512 EDMA events. Each of the parameter register sets consist of 8 32-bit word entries.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-17. EDMA Parameter Set RAM HEX ADDRESS RANGE DESCRIPTION 0x01C0 4000 - 0x01C0 401F Parameters Set 0 (8 32-bit words) 0x01C0 4020 - 0x01C0 403F Parameters Set 1 (8 32-bit words) 0x01C0 4040 - 0x01C0 405F Parameters Set 2 (8 32-bit words) 0x01C0 4060 - 0x01C0 407F Parameters Set 3 (8 32-bit words) 0x01C0 4080 - 0x01C0 409F Parameters Set 4 (8 32-bit words) 0x01C0 40A0 - 0x01C0 40BF Parameters Set 5 (8 32-bit words) ...
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 7.7 www.ti.com Reset The reset controller detects the different type of resets supported on the DM6467T device and manages the distribution of those resets throughout the device. The DM6467T device has several types of device-level global resets—power-on reset, warm reset, max reset, and system reset. Table 7-19 explains further the types of reset, the reset initiator, and the effects of each reset on the chip. See Section 7.7.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 When the POR pin is deasserted (high), the configuration pin values are latched and the PLL Controllers changed their system clocks to their default divide-down values. Both PLL Controllers are still in PLL Bypass Mode. Other device initialization also begins. 5. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 4. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles. At this point: – The I/O pins are controlled by the default peripherals (default peripherals are determined by PINMUX0 and PINMUX1 registers). – The clock and reset of each peripheral is determined by the default settings of the Power and Sleep Controller (PSC). – The PLL Controllers are operating in PLL Bypass Mode.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Test, emulation, clock, and power control logic are unaffected. The emulator initiates a System Reset via the C64x+ emulation logic. This reset can be masked by the emulator. This is the System Reset sequence: 1. The System Reset is initiated by the emulator. During this time, the following happens: – The reset signals flow to the entire chip resetting all the modules on chip, except the test and emulation logic.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 • • • www.ti.com Maximum Reset Warm Reset System Reset 7.7.7.1 Reset Type Status (RSTYPE) Register The Reset Type Status (RSTYPE) register (0x01C4 08E4) is the only register for the reset controller. This register falls in the same memory range as the PLL1 controller registers (see Table 7-11 for the PLL1 Controller Registers (Including Reset Controller)).
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Default Power Down Pins As discussed in Section 4.2, Power Considerations, the VDD3P3V_PWDN register controls power to the 3.3-V pins. The VDD3P3V_PWDN register defaults to powering down some 3.3-V pins to save power. For more details on the VDD3P3V_PWDN register and which 3.3-V pins default to power up or power down, see Section 4.2, Power Considerations. The pins that default to power down, are both reset to power down and high-impedance.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com All Other Pins During device reset, all other pins are controlled by the default peripheral. The default peripheral is determined by the default settings of the PINMUX0 or PINMUX1 registers. Some of the PINMUX0/PINMUX1 settings are determined by configuration pins latched at reset. To determine the reset behavior of these pins, see Section 4.
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TMS320DM6467T www.ti.com • SPRS605C – JULY 2009 – REVISED JUNE 2012 High Group: These pins are high by default, and remain high until configured otherwise by their respective peripheral (after the peripheral is enabled by the PSC).
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 7.7.9 www.ti.com Reset Electrical Data/Timing Note: If a configuration pin must be routed out from the device, the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon; TI recommends the use of an external pullup/pulldown resistor. Table 7-21. Timing Requirements for Reset (see Figure 7-19 and Figure 7-20) -1G NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Power Supplies Ramping Power Supplies Stable Clock Source Stable DEV_MXI (A) CLKOUT0 1 POR RESET SYSCLKREFCLK (PLLC1) 23 4 SYSCLKx 9 Boot and Configuration Pins Hi-Z 3 2 Config 10 DDR2 Z Group Hi-Z 11 DDR2 Low Group 12 DDR2 High Group 15 DDR2 Z/High Group Hi-Z 16 DDR2 Low/High Group 20 Z Group Hi-Z 21 Low Group 22 High Group A. B. Power supplies and DEV_MXI must be stable before the start of tW(RESET)..
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Power Supplies Stable DEV_MXI CLKOUT0 POR 1 RESET SYSCLKREFCLK (PLLC1) PLL1 CLOCK 23 4 SYSCLKx DIVx CLOCK 9 5 3 2 Hi-Z Boot and Configuration Pins Config 10 6 Hi-Z DDR2 Z Group 11 7 DDR2 Low Group 12 8 DDR2 High Group 13 DDR2 Z/High Group 15 Hi-Z 14 16 DDR2 Low/High Group 17 20 Hi-Z Z Group 18 21 19 22 Low Group High Group A.
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TMS320DM6467T www.ti.com 7.8 SPRS605C – JULY 2009 – REVISED JUNE 2012 Interrupts The DM6467T device has a large number of interrupts to service the needs of its many peripherals and subsystems. Both the ARM and C64x+ are capable of servicing these interrupts. All of the device interrupts are routed to the ARM interrupt controller with only a limited set routed to the C64x+ interrupt controller. The interrupts can be selectively enabled or disabled in either of the controllers.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-23.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-24.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 7.8.2 www.ti.com DSP Interrupts The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for each of the 12 CPU interrupts is user-programmable and is listed in Table 7-25. Also, the interrupt controller controls the generation of the CPU exception, NMI, and emulation interrupts. Table 7-26 summarizes the C64x+ interrupt controller registers and memory locations.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-25.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-26.
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TMS320DM6467T www.ti.com 7.9 SPRS605C – JULY 2009 – REVISED JUNE 2012 External Memory Interface (EMIF) DM6467T supports several memory and external device interfaces, including: • Asynchronous EMIF (EMIFA) for interfacing to NOR Flash, SRAM, etc. • NAND Flash • ATA (see Section 7.20, ATA Controller) 7.9.1 Asynchronous EMIF (EMIFA) The DM6467T Asynchronous EMIF (EMIFA) provides an 8-bit or 16-bit data bus, an address bus width up to 24 bits, and 4 chip selects, along with memory control signals.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-27.
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TMS320DM6467T www.ti.com 7.9.4 SPRS605C – JULY 2009 – REVISED JUNE 2012 EMIFA Electrical Data/Timing Table 7-28. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module (1) (see Figure 7-21 and Figure 7-22) -1G NO.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-29. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module (1) (2) (see Figure 7-21 and Figure 7-22) NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-29. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module(1) (2) (see Figure 7-21 and Figure 7-22) (continued) NO. 27 -1G PARAMETER th(EMWEH-EMDIV) MIN Output hold time, EM_WE high to EM_D[15:0] invalid MAX (WH + 1) * E - 3 (WH + 1) * E + 3 UNIT ns 3 1 EM_CS[5:2] EM_R/W EM_BA[1:0] EM_A[22:0] 4 8 5 9 6 7 10 EM_OE 13 12 EM_D[15:0] EM_WE Figure 7-21.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 15 1 EM_CS[5:2] EM_R/W EM_BA[1:0] EM_A[22:0] 16 17 18 19 20 21 24 22 23 EM_WE 27 26 EM_D[15:0] EM_OE Figure 7-22. Asynchronous Memory Write Timing for EMIF EM_CS[5:2] SETUP STROBE Extended Due to EM_WAIT STROBE HOLD EM_DQM[1:0] EM_BA[1:0] EM_A[22:0] EM_D[15:0] 14 11 EM_OE 2 EM_WAIT[5:2] Asserted 2 Deasserted Figure 7-23.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 EM_CS[5:2] SETUP STROBE Extended Due to EM_WAIT STROBE HOLD EM_DQM[1:0] EM_BA[1:0] EM_A[22:0] EM_D[15:0] 28 25 EM_WE 2 EM_WAIT[5:2] Asserted 2 Deasserted Figure 7-24.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.10 DDR2 Memory Controller The DDR2 Memory Controller is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM devices and can interface to either 16-bit or 32-bit DDR2 SDRAM devices. For details on the DDR2 Memory Controller, see the TMS320DM646x DMSoC DDR2 Memory Controller User's Guide (literature number SPRUEQ4). A memory map of the DDR2 Memory Controller registers is shown in Table 7-30. Table 7-30.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.10.1 DDR2 Memory Controller Electrical Data/Timing TI only supports board designs that follow the guidelines outlined in this document. Table 7-31. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory Controller (1) (2) (see Figure 7-25) NO. 1 2 (1) (2) -1G PARAMETER MIN MAX tc(DDR_CLK) Cycle time, DDR_CLK 2.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.10.2.3 PCB Stackup The minimum stackup required for routing the DM6467T is a six layer stack as shown in Table 7-33. Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size of the PCB footprint. Table 7-33.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Complete stack up specifications are provided in Table 7-34.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com DM646x DDR2 DDR_D0 DDR_D7 DDR_DQM0 DDR_DQS0 DQ0 T T DQ7 LDM LDQS T T LDQS DQ8 T DQ15 UDM UDQS UDQS T DDR_DQS0 DDR_D8 DDR_D15 DDR_DQM1 DDR_DQS1 DDR_DQS1 DDR_DQGATE0 DDR_DQGATE1 DDR_DQGATE2 DDR_DQGATE3 DDR_ODT0 DDR_D16 T T T T T T NC NC ODT (A) DDR_D23 DDR_DQM2 Vio 1.8 NC NC 1 KΩ DDR_D24 NC 1 KΩ DDR_D31 DDR_DQM3 DDR_DQS3 DDR_DQS3 NC NC DDR_DQS2 DDR_DQS2 (A) Vio 1.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-34. PCB Stack Up Specifications (continued) No.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-35. Placement Specifications No. Max Unit 1 Parameter X (1) (2) Min 1660 Mils 2 Y (1) (2) 1280 Mils 3 Y Offset (1) 650 Mils (2) (3) (4) 4 DDR2 Keepout Region 5 Clearance from non-DDR2 signal to DDR2 Keepout Region (5) (1) (2) (3) (4) (5) 4 w See Figure 7-26 for dimension defintions. Measurements from center of DSP device to center of DDR2 device.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.10.2.6 Bulk Bypass Capacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry. Table 7-36 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the DSP and DDR2 interfaces. Additional bulk bypass capacitance may be needed for other circuitry. Table 7-36. Bulk Bypass Capacitors No.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-38. Clock Net Class Definitions Clock Net Class DSP Pin Names CK DDR_DQS0/DDR_DQS0 DQS1 DDR_DQS1/DDR_DQS1 (1) DDR_DQS2/DDR_DQS2 DQS3 (1) DDR_DQS3/DDR_DQS3 DQS2 (1) DDR_CLK/DDR_CLK DQS0 Only used on 32-bit wide DDR2 memory systems. Table 7-39.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.10.2.10 VREF Routing VREF is used as a reference by the input buffers of the DDR2 memories as well as the DM6467T’s. VREF is intended to be 1/2 the DDR2 power supply voltage and should be created using a resistive divider as shown in Figure 7-27. Other methods of creating VREF are not recommended. Figure 7-30 shows the layout guidelines for VREF.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-41.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-42. DQS and DQ Routing Specification No.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-43. DQGATE Routing Specification No.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.11 Video Port Interface (VPIF) The DM6467T Video Port Interface (VPIF) allows the capture and display of digital video streams. Features include: • 150-MHz VPIF • Up to 2 Video Capture Channels (Channel 0 and Channel 1) – Two 8-bit Standard-Definition (SD) Video with embedded timing codes (BT.656) – Single 16-bit High-Definition (HD) Video with embedded timing codes (BT.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com VIDCLKCTL.VCH1CLK VP_CLKIN1 VP_CLKIN0 VP_CLKIN1 VP_CLKIN0 VPIF Channel 1 Input Clock Source 1 0 VSCLKDIS.VID1 Figure 7-35. VPIF Capture Channel 1 Source Clock Selection For both the dual 8-bit or 16-bit display modes, the VPIF Display Channel 2 outputs data synchronous to VP_CLKO2. The source clock for the VP_CLKO2 output is selectable from a number of external clock inputs or on-chip clock sources (see Figure 7-36). VIDCLKCTL.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 VIDCLKCTL.VCH3CLK VP_CLKIN3 VP_CLKIN3/TS1_CLKO VP_CLKIN2 VP_CLKIN2 STC_CLKIN GP[4]/STC_CLKIN VP_CLKIN0 VP_CLKIN0 AUXCLK PLL Controller 1 DEV_MXI/DEV_CLKIN CRG1_VCXI URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO SYSCLK8(A) 11x CRG0_VCXI 111 110 101 100 011 010 VPIF Channel 3 Output Clock Source 001 000 10x PINMUX0.CRGMUX VSCLKDIS.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.11.3 VPIF Register Descriptions Table 7-45 shows the VPIF registers. Table 7-45.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-45.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-45.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.11.4 VPIF Electrical Data/Timing Table 7-46. Timing Requirements for VPIF VP_CLKINx Inputs (1) (see Figure 7-38) -1G NO. MAX UNIT 1 tc(VKI) Cycle time, VP_CLKIN0/1/2/3 6.66 ns 2 tw(VKIH) Pulse duration, VP_CLKINx high 0.4C ns 3 tw(VKIL) Pulse duration, VP_CLKINx low 0.4C ns tt(VKI) Transition time, VP_CLKINx 4 (1) MIN 5 ns C = VP_CLKINx period in ns. 4 1 2 3 VP_CLKINx 4 Figure 7-38.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-47. Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs (see Figure 7-39) -1G NO. MIN 1 tsu(VDINV-VKIH) Setup time, VP_DINx valid before VP_CLKIN0/1 high 2 th(VKIH-VDINV) Hold time, VP_DINx valid after VP_CLKIN0/1 high MAX UNIT 1.98 ns 0 ns VP_CLKIN0/1 1 2 VP_DINx/FIELD/ HSYNC/VSYNC Figure 7-39. VPIF Channels 0/1 Video Capture Data and Control Input Timing Table 7-48.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.12 Transport Stream Interface (TSIF) The DM6467T device includes two independent Transport Stream Interfaces (TSIF0 and TSIF1) with corresponding Clock Reference Generator (CRGEN) Modules for System Time-Clock Recovery. The TSIF peripheral supports the following features: • 1-bit Serial and 8-bit Parallel independent receive and transmit interfaces with both synchronous and asynchronous modes. (TSIF1 supports Serial mode only.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.12.2 TSIF Clock Control The source clocks for the TSIF counters and output channels are selectable based on the settings of the TSIFCTL register (0x01C4 0050). (For more detailed information on the TSIFCTL register, see Section 4.3.2.2, TSIF Control.) The VSCLKDIS register (0x01C4 006C) is used to disable the clock inputs when changing the clock source to ensure glitch-free operation.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 TSIFCTL.TSIF0_CNTCLK VP_CLKIN1 VP_CLKIN1 VP_CLKIN0 100 CRG1_VCXI URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI AUXCLK PLL Controller 1 DEV_MXI/DEV_CLKIN 101 VP_CLKIN0 010 STC_CLKIN GP[4]/STC_CLKIN URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI TSIF0 Counter Clock 001 11x CRG0_VCXI UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO 011 000 10x PINMUX0.CRGMUX VSCLKDIS.TSIFCNT0 (A) 110, 111 = Reserved. Figure 7-42.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com TSIFCTL.TSIF1_CNTCLK VP_CLKIN3 VP_CLKIN3/TS1_CLKO VP_CLKIN2 VP_CLKIN2 URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO 11x CRG0_VCXI 10x 101 100 011 TSIF1 Counter Clock PINMUX0.CRGMUX AUXCLK PLL Controller 1 DEV_MXI/DEV_CLKIN STC_CLKIN GP[4]/STC_CLKIN CRG1_VCXI URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI 010 001 000 VSCLKDIS.TSIFCNT1 (A) 110, 111 = Reserved. Figure 7-44. TSIF1 Counter Clock Selection 7.12.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-50.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-50.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-51.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-51.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.12.4 Transport Stream Interface (TSIF) Electrical Data/Timing Table 7-52. Timing Requirements for TSIF Input (see Figure 7-45) -1G SERIAL INPUT NO.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-53. Switching Characteristics Over Recommended Operating Conditions for TSIF Output (see Figure 7-46) (continued) -1G SERIAL OUTPUT NO. 9 (4) td(TSCLKOV-TSDATAO) Delay time, TSx_CLKO edge to TSx_CTL/TSx_DATA (4) output valid PARALLEL OUTPUT (1) UNIT MIN MAX MIN MAX All Others 1 7.5 1 7.5 ns TS0_WAITO, TSx_EN_WAITO 1 16.5 1 16.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.13 Clock Recovery Generator (CRGEN) Each TSIF module has an associated CRGEN module which can adjust the local system time clock based upon the received Program Clock Reference (PCR) packets. CRGEN0 may only be used with TSIF 0 and CRGEN 1 may only be used with TSIF 1.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-55.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.13.2 CRGEN Electrical Data/Timing Table 7-56. Timing Requirements for CRGx_VCXI Input (see Figure 7-47) -1G NO. MIN NOM MAX 29.63 37.037 44.44 UNIT 1 tc(VCXI) Cycle time, CRGx_VCXI 2 tw(VCXIH) Pulse duration, CRGx_VCXI high 0.4P ns 3 tw(VCXIL) Pulse duration, CRGx_VCXI low 0.4P ns 4 tt(VCXI) Transition time, CRGx_VCXI 5 ns ns 4 1 2 3 CRGx_VCXI 4 Figure 7-47. CRGx_VCXI Input Timing Table 7-57.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.14 Video Data Conversion Engine (VDCE) The DM6467T Video Data Conversion Engine (VDCE) supports the following features: • Resize function on horizontal (HRSZ) and vertical (VRSZ) with ratio defined by 256/N (N is a natural number that ranges from 256 to 2048) with 4 taps interpolation. Magnification ratio of horizontal resize and vertical resize can be configured separately (different value can be configured).
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.14.2 VDCE Register Description(s) Table 7-59 shows the VDCE registers. Table 7-59.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-59.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.15 Peripheral Component Interconnect (PCI) The DM6467T DMSoC supports connections to PCI-compliant devices via the integrated PCI master/slave bus interface. The PCI port interfaces to DSP internal resources via the data switched central resource. The data switched central resource is described in more detail in Section 5, System Interconnect.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.15.2 PCI External Master Memory Map The PCI port includes a local DMA interface that allows external PCI master device intiated transfers to access the DM646x system bus. Table 7-61 shows the memory map for the PCI interface. Table 7-61.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.15.3 PCI Peripheral Register Description(s) Table 7-62.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-62. PCI Back End Configuration Registers (continued) DMSoC ACCESS HEX ADDRESS RANGE ACRONYM DMSoC ACCESS REGISTER NAME 01C1 A304 PCIMCFGADR PCI Master Configuration/IO Access Address Register 01C1 A308 PCIMCFGCMD PCI Master Configuration/IO Access Command Register 01C1 A30C - 01C1 A30F 01C1 A310 PCIMSTCFG Reserved PCI Master Configuration Register Table 7-63.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-64.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.15.4 PCI Electrical Data/Timing Texas Instruments (TI) has performed the simulation and system characterization to ensure that the PCI peripheral meets all AC timing specifications as required by the PCI Local Bus Specification Revision 2.3. Therefore, the AC timing specifications are not reproduced here. For more information on the AC timing specifications, see Section 4.2.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.16 Ethernet MAC (EMAC) The Ethernet Media Access Controller (EMAC) module provides an efficient interface between the DM6467T and the networked community. The EMAC supports 10Base-T (10 Mbits/second [Mbps]), and 100BaseTX (100 Mbps), in either half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode, with hardware flow control and quality-of-service (QOS) support.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.16.2 EMAC Bus Master Memory Map The EMAC control module includes a multi-channel DMA engine which is used to transfer receive and transmit packets between the EMAC and DM6467T memory. Table 7-66 shows the memory map for the EMAC DMA. Table 7-66.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.16.3 EMAC Peripheral Register Description(s) Table 7-67.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-67.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-67.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-68.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.16.4 EMAC Electrical Data/Timing Table 7-71. Timing Requirements for MRCLK - MII and GMII Operation (see Figure 7-49) -1G 1000 Mbps (GMII Only) NO. MIN MAX 100 Mbps 10 Mbps MIN MIN MAX UNIT MAX 1 tc(MRCLK) Cycle time, MRCLK 8 40 400 ns 2 tw(MRCLKH) Pulse duration, MRCLK high 2.8 14 140 ns 3 tw(MRCLKL) Pulse duration, MRCLK low 2.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 4 1 2 3 4 RFTCLK (Input) Figure 7-51.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-74. Switching Characteristics Over Recommended Operating Conditions for GMTCLK - GMII Operation (see Figure 7-52) -1G NO. PARAMETER 1000 Mbps MIN 1 tc(GMTCLK) Cycle time, GMTCLK 2 tw(GMTCLKH) 3 tw(GMTCLKL) 4 tt(GMTCLK) Transition time, GMTCLK UNIT MAX 8 ns Pulse duration, GMTCLK high 2.8 ns Pulse duration, GMTCLK low 2.8 ns 1 ns 4 1 2 4 3 GMTCLK (Output) Figure 7-52.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-76. Switching Characteristics Over Recommended Operating Conditions for EMAC MII and GMII Transmit 10/100 Mbit/s (1) (see Figure 7-54) -1G NO. 1 (1) PARAMETER td(MTCLKH-MTXD) 100/10 Mbps Delay time, MTCLK high to transmit selected signals valid UNIT MIN MAX 5 25 ns For MII, Transmit selected signals include: MTXD[3:0] and MTXEN. For GMII, Transmit selected signals include: MTXD[7:0] and MTXEN.
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TMS320DM6467T www.ti.com 7.17 SPRS605C – JULY 2009 – REVISED JUNE 2012 Management Data Input/Output (MDIO) The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and control Ethernet PHY(s) using a shared two-wire bus.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 7.17.2 www.ti.com Management Data Input/Output (MDIO) Electrical Data/Timing Table 7-79. Timing Requirements for MDIO Input (see Figure 7-56 and Figure 7-57) -1G NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.18 Host-Port Interface (HPI) Peripheral The HPI is a parallel port through which a host processor can directly access the CPU memory space. The host device functions as a master to the interface, which increases ease of access. The host and CPU can exchange information via internal or external memory. The host also has direct access to memory-mapped peripherals.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-81.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.18.4 HPI Electrical Data/Timing Table 7-83. Timing Requirements for Host-Port Interface Cycles (1) 61) (2) (see Figure 7-58 through Figure 7-1G NO.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-84. Switching Characteristics for Host-Port Interface Cycles (1) (see Figure 7-58 through Figure 7-61) NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 HCS HAS(D) 2 2 1 1 HCNTL[1:0] 2 1 2 1 HR/W 2 2 1 1 HHWIL 4 3 3 HSTROBE(A)(C) 15 15 14 14 6 8 HD[15:0] (output) 13 7 5 6 1st Half-Word 8 2nd Half-Word HRDY(B) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com HCS HAS(D) 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 3 3 4 HSTROBE(A)(C) 11 HD[15:0] (input) 11 12 12 1st Half-Word 5 13 2nd Half-Word 13 5 HRDY(B) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 HAS(D) (Input) 2 1 HCNTL[1:0] (input) HR/W (Input) 3 HSTROBE(A)(C) (Input) HCS (input) 14 15 8 6 HD[31:0] (output) 13 7 5 HRDY(B) (output) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com HAS(D) (input) 2 1 HCNTL[1:0] (input) HR/W (input) 3 HSTROBE(A)(C) (input) HCS (input) 12 11 HD[31:0] (input) 13 5 HRDY(B) (output) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.19 USB 2.0 [see Note] The DM6467T USB2.0 peripheral supports the following features: • USB 2.0 peripheral at speeds: high-speed (HS: 480 Mb/s) and full-speed (FS: 12 Mb/s) • USB 2.0 host at speeds HS, FS, and low speed (LS: 1.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-85. USB2.0 DMA Master Memory Map (continued) START ADDRESS END ADDRESS SIZE (BYTES) USB2.0 DMA ACCESS 0x8000 0000 0x9FFF FFFF 512M DDR2 Memory Controller 0xA000 0000 0xBFFF FFFF 512M Reserved 0xC000 0000 0xFFFF FFFF 1G Reserved 7.19.2 USB2.0 Device-Specific Information The DM6467T USBCTL register (0x01C4 00034) is part of the System Module Registers.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.19.3 USB2.0 Peripheral Register Description(s) Table 7-86 shows the USB perripheral register memory mapping. Table 7-86. USB2.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-86. USB2.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-86. USB2.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-86. USB2.0 Registers (continued) HEX ADDRESS RANGE ACRONYM COUNT0 0x01C6 4418 RXCOUNT REGISTER NAME Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) Number of bytes in host RX endpoint FIFO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-86. USB2.0 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C6 448C RXFUNCADDR Address of the target function that has to be accessed through the associated RX Endpoint 0x01C6 448E RXHUBADDR Address of the hub that has to be accessed through the associated RX Endpoint. This is used only when full-speed or low-speed device is connected via a USB2.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-86. USB2.0 Registers (continued) HEX ADDRESS RANGE 0x01C6 44A7 ACRONYM REGISTER NAME RXHUBPORT Port of the hub that has to be accessed through the associated RX Endpoint. This is used only when full-speed or low-speed device is connected via a USB2.0 high-speed hub.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-86. USB2.0 Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME Sets the operating speed, transaction protocol and peripheral endpoint number for the host TX endpoint.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.19.4 USB2.0 Electrical Data/Timing Table 7-87. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see Figure 7-62) -1G NO. LOW SPEED 1.5 Mbps PARAMETER FULL SPEED 12 Mbps HIGH SPEED 480 Mbps MIN MAX MIN MAX MIN 1 tr(D) Rise time, USB_DP and USB_DN signals (1) 75 300 4 20 0.5 2 tf(D) Fall time, USB_DP and USB_DN signals (1) 75 300 4 20 0.
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TMS320DM6467T www.ti.com 7.20 SPRS605C – JULY 2009 – REVISED JUNE 2012 ATA Controller The ATA peripheral supports the following features: • PIO, multiword DMA, and Ultra ATA 33/66/100 • Up to mode 4 timings on PIO mode • Up to mode 2 timings on multiword DMA • Up to mode 5 timings on Ultra ATA • Programmable timing parameters • Supports TrueIDE mode for Compact Flash 7.20.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.20.2 ATA Peripheral Register Description(s) Table 7-89 shows the ATA registers. Table 7-89.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.20.3 ATA Electrical Data/Timing All ATA AC timing data described in Section 7.20.3.1 – Section 7.20.3.3 is provided at the DM6467T device pins. For more details, see Section 7.1, Parameter Information. The AC timing specifications described in Section 7.20.3.1 – Section 7.20.3.3 assume correct configuration of the ATA memory-mapped control registers for the selected ATA frequency of operation. 7.20.3.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com t0 DA[2:0], ATA_CS0, ATA_CS1 t1 t2 t9 DIOW/DIOR t2i t3 t4 DD[15:0](OUT) t6 t5 DD[15:0] (IN) t6Z IORDY(A) tA tRD tC IORDY(B) tC IORDY(C) tB A. IORDY is not negated for transfer (no wait generated) B. IORDY is negative but is re-asserted before tA (no wait is generated) C. IORDY is negative before tA and remains asserted until tB; data is driven valid at tRD (wait is generated) Figure 7-64.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.20.3.2 ATA Multiword DMA Timing Table 7-91. Timings for ATA Module — Multiword DMA AC Timing (1) (2) (see Figure 7-65) -1G NO. MODE MIN 1 t0 Cycle time 0-2 (DMASTB + DMARCVR + 2)P - 0.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com DA[2:0], ATA_CS0, ATA_CS1 t0 tM tN DMARQ tL DMACK tI tD tK DIOW/DIOR tJ tH tG DD[15:0](OUT) tG tE tF tZ DD[15:0] (IN) Figure 7-65.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.20.3.3 ATA Ultra DMA Timing Table 7-92. Timings for ATA Module — Ultra DMA AC Timing (1) (see Figure 7-66 through Figure 7-75) -1G NO.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-92. Timings for ATA Module — Ultra DMA AC Timing(1) (2) (see Figure 7-66 through Figure 7-75) (continued) -1G NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 DMARQ tUI DMACK tFS tACK tENV tZAD STOP (DIOW) (A) tACK tENV HDMARDY (DIOR) (A) tFS tZIORDY tZAD tZFS DSTROBE (IORDY) (A) tDZFS tAZ tDVS tDVH DD[15:0] tACK DA[2:0], ATA_CS0, ATA_CS1 A. The definitions for the DIOW:STOP, DIOR:HDMARDY, and IORDY:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 7-66.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com DMARQ DMACK STOP (DIOW) tRP HDMARDY (DIOR) tRFS DSTROBE (IORDY) DD[15:0] Figure 7-68. ATA Host Pausing an Ultra DMA Data-In Burst Timing DMARQ tMLI DMACK tLI tACK tLI STOP (DIOW) tLI tACK HDMARDY (DIOR) tSS tIORDYZ DSTROBE (IORDY) tZAH tAZ DD[15:0] DA[2:0], ATA_CS0, ATA_CS1 tCVH tCVS CRC tACK Figure 7-69.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 DMARQ tLI tMLI DMACK tACK tRP STOP (DIOW) tZAH tACK tAZ HDMARDY (DIOR) tLI tRFS tMLI tIORDYZ DSTROBE (IORDY) tCVS tCVH CRC DD[15:0] tACK DA[2:0], ATA_CS0, ATA_CS1 Figure 7-70. ATA Host Terminating an Ultra DMA Data-In Burst Timing DMARQ tUI DMACK tACK tENV STOP (DIOW) (A) tLI tZIORDY tUI DDMARDY (IORDY) (A) tACK HSTROBE (DIOR) (A) tDZFS tDVS tDVH DD[15:0] DA[2:0], ATA_CS0, ATA_CS1 A.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com t2CYC t2CYC tCYC(A) tCYC(A) HSTROBE (DIOR) tDVS tDVH tDVH tDVS tDVH DD[15:0] (OUT) A. While HSTROBE (DIOR) timing is tCYC at the host, it may be different at the device due to propagation delay differences on the cable. Figure 7-72. ATA Sustained Ultra DMA Data-Out Transfer Timing DMARQ tRP DMACK STOP (DIOW) DDMARDY (IORDY) tRFS HSTROBE (DIOR) DD[15:0] Figure 7-73.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 tLI DMARQ tMLI DMACK tLI STOP (DIOW) tACK tSS tLI tIORDYZ DDMARDY (IORDY) tACK HSTROBE (DIOR) tCVS tCVH DD[15:0] CRC tACK DA[2:0], ATA_CS0, ATA_CS1 Figure 7-74. ATA Host Terminating an Ultra DMA Data-Out Burst Timing DMARQ DMACK tLI tACK tMLI STOP (DIOW) tRP tIORDYZ DDMARDY (IORDY) tRFS tLI tACK tMLI HSTROBE (DIOR) tCVS tCVH DD[15:0] CRC tACK DA[2:0], ATA_CS0, ATA_CS1 Figure 7-75.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.20.3.4 ATA HDDIR Timing Figure 7-76 through Figure 7-79 show the behavior of HDDIR for the different types of transfers. Table 7-93. Timing Requirements for HDDIR (1) -1G NO. 1 (1) MIN tc Cycle time, ATA_CS[1:0] to HDDIR low E - 3.1 MAX UNIT ns E = ATA clock cycle DA[2:0], ATA_CS0, ATA_CS1 tC(A) tC(A) HDDIR DIOW DD[15:0] (OUT) A. tC ≥ one cycle Figure 7-76.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 DA[2:0], ATA_CS0, ATA_CS1 DMACK tC(A) tC(A) HDDIR DIOW DD[15:0] (OUT) A. tC ≥ one cycle Figure 7-78. ATA HDDIR Multiword DMA Write Transfer Timing DA[2:0], ATA_CS0, ATA_CS1 DMACK tC(A) HDDIR DIOW DD[15:0] (OUT) CRC A. tC ≥ one cycle Figure 7-79.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.21 VLYNQ The DM6467T VLYNQ peripheral provides a high speed serial communications interface with the following features.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-94.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-95.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.21.3 VLYNQ Electrical Data/Timing Table 7-96. Timing Requirements for VLYNQ_CLOCK Input (see Figure 7-80) -1G NO. MIN MAX UNIT 1 tc(VCLK) Cycle time, VLYNQ_CLOCK 9.6 ns 2 tw(VCLKH) Pulse duration, VLYNQ_CLOCK high 3 ns 3 tw(VCLKL) Pulse duration, VLYNQ_CLK low 3 4 tt(VCLK) Transition time, VLYNQ_CLOCK ns 3 ns Table 7-97.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-99. Timing Requirements for Receive Data for the VLYNQ Module (1) (see Figure 7-81) -1G NO. 3 4 (1) MIN tsu(RXDV-VCLKH) th(VCLKH-RXDV) MAX UNIT Setup time, VLYNQ_RXD[3:0] valid before RTM disabled, RTM sample = 3 VLYNQ_CLOCK high RTM enabled 0.
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TMS320DM6467T www.ti.com 7.22 SPRS605C – JULY 2009 – REVISED JUNE 2012 Multichannel Audio Serial Port (McASP0/1) Peripherals The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission (DIT). 7.22.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 7.22.2 www.ti.com McASP0 and McASP1 Peripheral Register Description(s) Table 7-101.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-101.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-102. McASP0 Data Registers HEX ADDRESS RANGE 01D0 1400 – 01D0 17FF 302 ACRONYM RBUF0/XBUF0 REGISTER NAME McASP0 receive buffers or McASP0 transmit buffers via the Peripheral Data Bus. COMMENTS (Used when RSEL or XSEL bits = 0 [these bits are located in the RFMT or XFMT registers, respectively].
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-103.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-103.
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TMS320DM6467T www.ti.com 7.22.3 SPRS605C – JULY 2009 – REVISED JUNE 2012 McASP0 and McASP1 Electrical Data/Timing 7.22.3.1 Multichannel Audio Serial Port (McASP0) Timing Table 7-105. Timing Requirements for McASP0 (see Figure 7-82 and Figure 7-83) (1) -1G NO.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-106. Switching Characteristics Over Recommended Operating Conditions for McASP0 (1) (see Figure 7-82 and Figure 7-83) NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 2 1 2 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 4 3 4 ACLKR/X (CLKRP = CLKXP = 0)(A) ACLKR/X (CLKRP = CLKXP = 1)(B) 6 5 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 8 7 AXR[n] (Data In/Receive) A. B.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 10 10 9 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 12 11 12 ACLKR/X (CLKRP = CLKXP = 1)(A) ACLKR/X (CLKRP = CLKXP = 0)(B) 13 13 13 13 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) 13 13 13 AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 14 15 AXR[n] (Data Out/Transmit) A0 A. B.
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TMS320DM6467T www.ti.com 7.22.3.2 SPRS605C – JULY 2009 – REVISED JUNE 2012 Multichannel Audio Serial Port (McASP1) DIT Timing Table 7-107. Timing Requirements for McASP1 (see Figure 7-82 and Figure 7-83) (1) -1G NO. (1) MIN 1 tc(AHCKRX) Cycle time, AHCLKX 2 tw(AHCKRX) Pulse duration, AHCLKX high or low 3 tc(CKRX) Cycle time, ACLKX 4 tw(CKRX) Pulse duration, ACLKX high or low MAX UNIT 20.8 ns 8.3 ns ACLKX ext 37 ns ACLKX ext 15 ns ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-108. Switching Characteristics Over Recommended Operating Conditions for McASP1 (1) (see Figure 7-82 and Figure 7-83) NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.23 Serial Peripheral Interface (SPI) The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (2-to-16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communication between the TMS320DM646x DMSoC and external peripherals.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.23.3 SPI Electrical Data/Timing Master Mode — General Table 7-110. General Switching Characteristics in Master Mode (1) NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-111. General Input Timing Requirements in Master Mode -1G NO.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Slave Mode — General Table 7-112. General Switching Characteristics in Slave Mode (For 3-/4-/5-Pin Modes) (1) NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-113. General Input Timing Requirements in Slave Mode (1) -1G NO.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Master Mode — Additional Table 7-114. Additional Output Switching Characteristics of 4-Pin Enable Option in Master Mode (1) NO. 17 (1) (2) PARAMETER td(EN-CLK) -1G MIN MAX Delay time, slave assertion of SPI_EN active to first SPI_CLK rising edge from master, 4-pin mode, polarity = 0, phase = 0 3P + 6 Delay time, slave assertion of SPI_EN active to first SPI_CLK rising edge from master, 4-pin mode, polarity = 0, phase = 1 0.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-116. Additional Output Switching Characteristics of 4-Pin Chip-Select Option in Master Mode (1) (2) NO. 19 20 (1) (2) (3) -1G PARAMETER tosu(CS-CLK) td(CLK-CS) (3) MIN MAX Output setup time, SPI_CS[n] active before first SPI_CLK rising edge, polarity = 0, phase = 0, SPIDELAY.C2TDELAY = 0 (C2TDELAY + 2) * P - 6 Output setup time, SPI_CS[n] active before first SPI_CLK rising edge, polarity = 0, phase = 1, SPIDELAY.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-117. Additional Output Switching Characteristics of 5-Pin Option in Master Mode (1) NO. 32 22 23 (1) (2) (3) 318 PARAMETER td(CLK-CS) (2) tosu(CS-CLK) td(CLK-EN) (2) (3) (2) -1G MIN Delay time, final SPI_CLK falling edge to master deasserting SPI_CS[n], polarity = 0, phase = 0, SPIDELAY.T2CDELAY = 0, SPIDAT1.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-118. Additional Input Timing Requirements of 5-Pin Option in Master Mode (1) -1G NO. 21 td(CSL-ENA) 31 (1) (2) (3) MIN td(CLK-ENA) (2) (3) MAX MIN UNIT MAX Delay time, max delay for slave SPI to drive SPI_ENA valid after master asserts SPI_CS[n] to delay the master from beginning the next transfer 0.5P 0.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-121. Additional Input Timing Requirements of 4-Pin Chip-Select Option in Slave Mode (1) -1G NO. MIN 25 26 (1) (2) Setup time, SPI_CS[n] asserted at slave to first SPI_CLK edge (rising or falling) at slave tsu(CSL-CLK) td(CLK-CSH) (2) MAX 2P + 6 Delay time, final falling edge SPI_CLK to SPI_CS[n] deasserted, polarity = 0, phase = 0 0.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-122. Additional Output Switching Characteristics of 5-Pin Option in Slave Mode(1) (continued) NO. 38 39 PARAMETER td(CLK-ENZ) td(CSH-ENH) (2) (2) -1G MIN UNIT MAX Delay time, final clock receive edge on SPI_CLK to slave deasserting SPI_EN, polarity = 0, phase = 0, SPIINT0.ENABLE HIGHZ = 0 3P + 15 Delay time, final clock receive edge on SPI_CLK to slave deasserting SPI_EN, polarity = 0, phase = 1, SPIINT0.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.
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TMS320DM6467T www.ti.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com MASTER MODE 4 PIN WITH ENABLE 18 17 SPI_CLK MO(0) SPI_SIMO MO(1) MI(1) MI(0) SPI_SOMI MO(n-1) MI(n-1) MO(n) MI(n) SPI_EN MASTER MODE 4 PIN WITH CHIP SELECT 20 19 SPI_CLK MO(0) SPI_SIMO MO(1) MI(0) SPI_SOMI MI(1) MO(n-1) MI(n-1) MO(n) MI(n) SPI_CS[n] MASTER MODE 5 PIN 22 32 23 31 SPI_CLK SPI_SIMO MO(0) MI(0) SPI_SOMI MO(1) MO(n-1) MO(n) MI(1) MI(n-1) MI(n) 21 SPI_EN DESEL(A) DESEL(A) SPI_CS[n] A.
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TMS320DM6467T www.ti.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.24 Universal Asynchronouse Receiver/Transmitter (UART) The UART performs serial-to-parallel conversions on data received from a peripheral device and parallelto-serial conversion on data received from the CPU. 7.24.1 UART Device-Specific Information DM6467T provides up to 3 UART peripheral interfaces depending on the selected pin multiplexing.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.24.2 UART Peripheral Register Description(s) Table 7-124 shows the UART register name summary. Table 7-125, Table 7-126, and Table 7-127 show the UART0/1/2 registers, respectively along with their configuration requirements. Table 7-124.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-125.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 Table 7-126.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-127.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.24.3 UART Electrical Data/Timing [Receive/Transmit] Table 7-128. Timing Requirements for UARTx Receive (1) (see Figure 7-88) -1G NO. (1) MIN MAX UNIT 4 tw(URXDB) Pulse duration, receive data bit (URXDx) [15/30/100 pF] 0.96U 1.05U ns 5 tw(URXSB) Pulse duration, receive start bit [15/30/100 pF] 0.96U 1.05U ns U = UART baud time = 1/programmed baud rate. Table 7-129.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.24.4 IrDA Interface Receive/Transmit Timings Table 7-130. Signaling Rate and Pulse Duration Specification in Receive Mode SIGNALING RATE ELECTRICAL PULSE DURATION MAX NOM MIN UNIT SIR MODE 2.4 Kbit/s (Kbps) 1.41 78.1 88.55 μs 9.6 Kbps 1.41 19.5 22.13 μs 19.2 Kbps 1.41 9.75 11.07 μs 38.4 Kbps 1.41 4.87 5.96 μs 57.6 Kbps 1.41 3.25 4.34 μs 115.2 Kbps 1.41 1.62 2.23 μs 416 518.8 ns MIR MODE 0.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.25 Inter-Integrated Circuit (I2C) The inter-integrated circuit (I2C) module provides an interface between DM6467T and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External components attached to this 2-wire serial bus can transmit/receive 2 to 8-bit data to/from the DMSoC through the I2C module. The I2C port does not support CBUS compatible devices.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 7.25.1 www.ti.com I2C Peripheral Register Description(s) Table 7-133.
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TMS320DM6467T www.ti.com 7.25.2 SPRS605C – JULY 2009 – REVISED JUNE 2012 I2C Electrical Data/Timing Table 7-134. Timing Requirements for I2C Timings (1) (see Figure 7-89) -1G STANDARD MODE NO. MIN 1 (1) (2) (3) (4) (5) FAST MODE MAX MIN UNIT MAX tc(SCL) Cycle time, SCL 10 2.5 µs 2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs 3 th(SCLL-SDAL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-135. Switching Characteristics for I2C Timings (1) (see Figure 7-90) -1G NO. STANDARD MODE PARAMETER MIN 16 MAX FAST MODE MIN UNIT MAX tc(SCL) Cycle time, SCL 10 2.5 µs 17 td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) 4.7 0.6 µs 18 td(SDAL-SCLL) Delay time, SDA low to SCL low (for a START and a repeated START condition) 4 0.6 µs 19 tw(SCLL) Pulse duration, SCL low 4.7 1.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.26 Pulse Width Modulator (PWM) The PWM provides a way to generate a pulse periodic waveform for motor control or can act as a digitalto-analog converter with some external components. 7.26.1 PWM Device-Specific Information The 2 DM6467T Pulse Width Modulator (PWM) peripherals support the following features: • 32-bit period counter • 32-bit first-phase duration counter • 32-bit repeat count for one-shot operation.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.26.3 PWM0/1 Electrical Data/Timing Table 7-138. Switching Characteristics Over Recommended Operating Conditions for PWM0/1 Outputs (1) (see Figure 7-91 and Figure 7-92) NO.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.27 Timers The timers support four modes of operation: a 64-bit general-purpose (GP) timer, dual-unchained 32-bit GP timers, dual-chained 32-bit timers, or a watchdog timer. The GP timer mode can be used to generate periodic interrupts or EDMA synchronization events. The watchdog timer mode is used to provide a recovery mechanism for the device in the event of a fault condition, such as a non-exiting code loop. 7.27.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-140.
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TMS320DM6467T www.ti.com 7.27.3 SPRS605C – JULY 2009 – REVISED JUNE 2012 Timer Electrical Data/Timing Table 7-142. Timing Requirements for Timer Input (1) (see Figure 7-93) -1G NO. (1) MIN MAX UNIT 1 tw(TINPH) Pulse duration, TINPxL/TINP0U high 2P ns 2 tw(TINPL) Pulse duration, TINPxL/TINP0U low 2P ns P = DEV_MXI/DEV_CLKIN cycle time in ns. For example, when DEV_MXI/DEV_CLKIN frequency is 27 MHz, use P = 37.037 ns. Table 7-143.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 7.28 General-Purpose Input/Output (GPIO) The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. When configured as an output, a write to an internal register can control the state driven on the output pin. When configured as an input, the state of the input is detectable by reading the state of an internal register.
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TMS320DM6467T www.ti.com 7.28.2 SPRS605C – JULY 2009 – REVISED JUNE 2012 GPIO Peripheral Register Description(s) Table 7-144 shows the GPIO peripheral registers. Table 7-144.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 7.28.3 www.ti.com GPIO Peripheral Input/Output Electrical Data/Timing Table 7-145. Timing Requirements for GPIO Inputs (1) (see Figure 7-94) -1G NO. MIN MAX UNIT 1 tw(GPIH) Pulse duration, GP[x] input high 2C (2) ns 2 tw(GPIL) Pulse duration, GP[x] input low 2C (2) ns (1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 7.29 IEEE 1149.1 JTAG The JTAG (3) interface is used for BSDL testing and emulation of the DM6467T device. TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE correctly.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com Table 7-148. JTAG ID Register Selection Bit Descriptions BIT NAME 31:28 VARIANT 27:12 PART NUMBER 11-1 MANUFACTURER 0 LSB 7.29.2 DESCRIPTION Variant (4-Bit) value. DM6467T value: 0001 [Silicon Revision 3.0 and later]. Part Number (16-Bit) value. DM6467T value: 1011 0111 0111 0000. Manufacturer (11-Bit) value. DM6467T value: 0000 0010 111. LSB. This bit is read as a "1" for DM6467T.
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TMS320DM6467T www.ti.com SPRS605C – JULY 2009 – REVISED JUNE 2012 1 2 3 TCK 4 5 6 RTCK 11 TDO 8 7 TDI/TMS/TRST 10 9 EMU[1:0](Input) 12 EMU[1:0](Output) Figure 7-96.
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TMS320DM6467T SPRS605C – JULY 2009 – REVISED JUNE 2012 www.ti.com 8 Mechanical Packaging and Orderable Information The following table(s) show the thermal resistance characteristics for the PBGA–CUT mechanical package. 8.1 Thermal Data for CUT Table 8-1. Thermal Resistance Characteristics (PBGA Package) [CUT] NO. °C/W (1) AIR FLOW (m/s) (2) N/A 1 RΘJC Junction-to-case 1.5 2 RΘJB Junction-to-board 9.9 N/A 3 RΘJA Junction-to-free air 19.2 0.00 4 14.8 0.50 5 13.8 1.00 12.7 2.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 8-Feb-2014 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
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