Datasheet

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TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
The L2 memory configuration for the C6472 device is as follows:
• Port 0 configuration:
– Memory size is 608KB
– Starting address is 0080 0000h
– 2-cycle latency
– 4 × 128-bit bank configuration
• Port 1 configuration:
– Memory size 768K ROM, starting address is 0010 0000h
– Memory size is 768KB shared RAM, starting address is 0020 0000h
– 1-cycle latency
– 4 × 256-bit bank configuration
Table 5-1. SL2 Prefetch Enabled Memory Regions
HEX ADDRESS RANGE DESCRIPTION
ROM
0010 0000 - 0010 FFFF Shared Memory Controller Page 0
0011 0000 - 0011 FFFF Shared Memory Controller Page 1
0012 0000 - 0012 FFFF Shared Memory Controller Page 2
0013 0000 - 0013 FFFF Shared Memory Controller Page 3
0014 0000 - 0014 FFFF Shared Memory Controller Page 4
0015 0000 - 0015 FFFF Shared Memory Controller Page 5
0016 0000 - 0016 FFFF Shared Memory Controller Page 6
0017 0000 - 0017 FFFF Shared Memory Controller Page 7
0018 0000 - 0018 FFFF Shared Memory Controller Page 8
0019 0000 - 0019 FFFF Shared Memory Controller Page 9
001A 0000 - 001A FFFF Shared Memory Controller Page 10
001B 0000 - 001B FFFF Shared Memory Controller Page 11
001C 0000 - 001F FFFF Reserved
RAM
0020 0000 - 0020 FFFF Shared Memory Controller Page 16
0021 0000 - 0021 FFFF Shared Memory Controller Page 17
0022 0000 - 0022 FFFF Shared Memory Controller Page 18
0023 0000 - 0023 FFFF Shared Memory Controller Page 19
0024 0000 - 0024 FFFF Shared Memory Controller Page 20
0025 0000 - 0025 FFFF Shared Memory Controller Page 21
0026 0000 - 0026 FFFF Shared Memory Controller Page 22
0027 0000 - 0027 FFFF Shared Memory Controller Page 23
0028 0000 - 0028 FFFF Shared Memory Controller Page 24
0029 0000 - 0029 FFFF Shared Memory Controller Page 25
002A 0000 - 002A FFFF Shared Memory Controller Page 26
002B 0000 - 002B FFFF Shared Memory Controller Page 27
002C 0000 - 002F FFFF Reserved
98 C64x+ Megamodule Copyright © 2009–2011, Texas Instruments Incorporated
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