Datasheet

PRODUCTPREVIEW
CPU/3
32-bit
CFGSCR
DMA
SCR
M
32
S
C64x+
Megamodule_0
M
M
M
M
M
M
S
S
S
S
S
S
M
Bridge
32
S
BOOTCtl
S
PSC
S
SMC
S
SMCP x6
S
EMC1
S
EMIC0
32
32
32
32
32
32
S
ETBx6
M
Bridge
32
HPI
S
Timer64x12
S
IIC
S
SEC_CTL
S
EMACMDIO
S
Chip-Level
Registers
S
S
PLLCrtl(1,2,3)
S
GPIO
M
Bridge
32
S
EMAC0
DescMem
S
M
Bridge
32
EMAC1
S
EMAC0
S
3xTSIP
S
S
PDMA
S
UTOPIA
M
Bridge
32
SRIO
S
S
M
Bridge
32
3PTC1
S
3PTC2
S
3PTC3
S
S
3PCC
S
3PTC0
M
C64x+
Megamodule_1
C64x+
Megamodule_2
C64x+
Megamodule_3
C64x+
Megamodule_4
C64x+
Megamodule_5
SCR
CPU/6
EMAC1
DescMem
SRIO
DescMem
SCR
CPU/6
SCR
CPU/3
SCR
CPU/3
SCR
CPU/3
SCR
CPU/3
TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
Figure 4-3. Configuration Switched Central Resource
Copyright © 2009–2011, Texas Instruments Incorporated System Interconnect 95
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