Datasheet

PRODUCTPREVIEW
EDMA3
Channel
Controller
EDMA3
Transfer
Controllers
CPU/3
128-bit
DMA SCR
ChipEvents
EMAC1
EMAC0
UTOPIA
Bridge
Bridge
Bridge
Bridge
M
M
M
M
M
M
M
M
HPI
M
M
M
M
32
M
32
32
128
128
128
128
S
S
S
S
S
S
S
S
S
128
128
128
128
128
128
128
128
128
Bridge
TSIP0 M
128
32
TSIP1
M
32
TSIP2
M
32
NET
SCR
SRIO
M
32
SRIO
M
128
Bridge
128
128
S
S
M
128
M
128
M
128
M
128
M
128
M
128
S
S
S
S
S
S
M
Bridge
32
S
128
CFG
SCR
M
128
S
DDR
PDMA
TDM
SCR
SRIO
SCR
M
128
S
M
128
S
M
128
S
M
128
S
M
128
S
M
128
S
C64x+
Megamodule_0
C64x+
Megamodule_1
C64x+
Megamodule_2
C64x+
Megamodule_3
C64x+
Megamodule_4
C64x+
Megamodule_5
SRIO
C64x+
Megamodule_0
C64x+
Megamodule_1
C64x+
Megamodule_2
C64x+
Megamodule_3
C64x+
Megamodule_4
C64x+
Megamodule_5
Xconn1_M
Xconn2_M
32
M
M
S
S
128
128
TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
Figure 4-1. DMA Switched Central Resource
92 System Interconnect Copyright © 2009–2011, Texas Instruments Incorporated
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