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TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
3.9.5 DSP_BOOT_ADDRn Register (DSP_BOOT_ADDR0-DSP_BOOT_ADDR5)
Each C64x+ megamodule has its own boot address register (DSP_BOOT_ADDRn) associated with it. The
contents of these registers are the 22 MSBs of the initial fetch address of the C64x+ megamodulen from
where it starts executing after the boot complete bit is set.
In Immediate Boot (Boot mode 0) and HPI Boot (Boot mode 1) modes, all six registers have the L2 RAM
base address tie-off value 00 2000h as default, which corresponds to 0080 0000h. In the case of HPI boot
mode, the host can overwrite these registers before boot complete is set to change the boot address for
each C64x+ megamodule.
For other boot modes (boot modes 2 - 15), DSP_BOOT_ADDR0 has SL2 ROM base address tie-off value
00 0400h as the default. Other GEM_BOOT_ADDRn registers have L2 RAM base address tie-off values
00 2000h as default. In this mode, the application can set individual boot addresses for individual C64x+
megamodules by programming different values in the GEM_BOOT_ADDRn registers.
31 22 21 16
Reserved DSP_BOOT_ADDR
(A)
R-0 R/W-00 0000 0010 0000 0000 0000
15 0
DSP_BOOT_ADDR
(A)
R/W-00 0000 0010 0000 0000 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
A. For boot modes 2 - 15, DSP_BOOT_ADDR0 has default address 00 0400h and DSP_BOOT_ADDR1 - DSP_BOOT_ADDR5 have
default address 00 2000h. For boot mode 0 and 1, all registers have default address 00 2000h.
Figure 3-19. DSP_BOOT_ADDRn Register (DSP_BOOT_ADDR0-DSP_BOOT_ADDR5)
Table 3-23. DSP_BOOT_ADDRn Register (DSP_BOOT_ADDR0-DSP_BOOT_ADDR5) Field
Descriptions
Bit Field Value Description
31:22 Reserved Reserved
21:0 DSP_BOOT_ADDR DSP Boot Address.
(1)
(1) For boot modes 2 - 15, DSP_BOOT_ADDR0 has default address 00 0400h and DSP_BOOT_ADDR1 - DSP_BOOT_ADDR5 have
default address 00 2000h. For boot mode 0 and 1, all registers have default address 00 2000h.
88 Device Configuration Copyright © 2009–2011, Texas Instruments Incorporated
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