Datasheet

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TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
3.6.2 Memory Privilege Permission Register (PRIVPERM)
The memory privilege permission register (PRIVPERM) defines the permission level necessary to access
peripheral registers on the CFG SCR. The defaults allow both user- and supervisor-level accesses to
these peripheral groups. If desired, the software can override accesses to these peripheral groups by
writing the values shown in Table 3-11 to the register bits. For the purposes of protection, certain
peripherals are grouped together (see Table 3-12), thus, the selected protection applies to the entire
group; i.e., setting 0 to the RIO bit field would make user-mode accesses to SRIO and SRIO wrappers
configuration space.
Table 3-11. Permission Values
ACCESSES PERMISSION VALUE
Supervisor and user modes 00
Supervisor mode 10
User mode 01
None 11
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO HPI EMAC UTOPIA RIO TSIP TIMER64 IIC
R/W-00 R/W-00 R/W-00 R/W-00 R/W-00 R/W-00 R/W-00 R/W-00
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMC CLRF1 CLRF0 PLL_CTRL PSC SEC_CTL BOOT_CTL ETB
R/W-00 R/W-00 R/W-0, R-0 R/W-00 R/W-00 R/W-00 R/W-00 R/W-00
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-6. Memory Privilege Permission Register (PRIVPERM)
Table 3-12. PRIVPERM Register Peripheral Grouping
PERIPHERAL GROUP GROUP CONTENTS
GPIO GPIO module
HPI HPI module
EMAC EMAC0, EMAC1, MDIO, EMAC0 Descriptor Memory, EMIC0, EMAC1
Descriptor Memory, EMIC1
UTOPIA UTOPIA, PIM-PDMA
RIO SRIO, SRIO Descriptor Memory
TSIP TSIP2, TSIP1, TSIP0
TIMER64 12 Timer64s
IIC IIC
SMC SMC and 6 SMCPs
CLRF1 Chip-level register file class 1
CLRF0 Chip-level register file class 0
PLL_CTRL PLL1, PLL2, and PLL3 controllers
PSC Power and sleep controllers
SEC_CTL Security control
BOOT_CTL Boot controller
ETB 6 ETBs
76 Device Configuration Copyright © 2009–2011, Texas Instruments Incorporated
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