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TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
SPRU862 TMS320C64x+ DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the
TMS320C64x+ digital signal processor (DSP) of the TMS320C6000 DSP family can be
efficiently used in DSP applications. Shows how to maintain coherence with external
memory, how to use DMA to reduce memory latencies, and how to optimize your code to
improve cache efficiency. The internal memory architecture in the C64x+ DSP is organized
in a two-level hierarchy consisting of a dedicated program cache (L1P) and a dedicated data
cache (L1D) on the first level. Accesses by the CPU to the these first level caches can
complete without CPU pipeline stalls. If the data requested by the CPU is not contained in
cache, it is fetched from the next lower memory level, L2 or external memory.
SPRU395 TMS320C64x Technical Overview. Provides an introduction to the TMS320C64x digital
signal processors (DSPs) of the TMS320C6000 DSP family.
SPRU198 TMS320C6000 Programmer's Guide. Reference for programming the TMS320C6000 digital
signal processors (DSPs). Before you use this manual, you should install your code
generation and debugging tools. Includes a brief description of the C6000 DSP architecture
and code development flow, includes C code examples and discusses optimization methods
for the C code, describes the structure of assembly code and includes examples and
discusses optimizations for the assembly code, and describes programming considerations
for the C64x DSP.
SPRUEC6 TMS320C645x/C647x Bootloader User's Guide. This document describes the features of
the on-chip bootloader provided with the TMS320C645x/C647x Digital Signal Processors
(DSPs).
SPRU806 TMS320C6472/TMS320TCI648x DSP Software-Programmable Phase-Locked Loop
(PLL) Controller User's Guide. This document describes the operation of the
software-programmable phase-locked loop (PLL) controller in the
TMS320C6472/TMS320TCI648x digital signal processors (DSPs). The PLL controller offers
flexibility and convenience by way of software-configurable multiplier and dividers to modify
the input signal internally. The resulting clock outputs are passed to the C6472/TCI648x DSP
core, peripherals, and other modules inside the C6472/TCI648x DSP.
SPRUEG1 TMS320C6472/TMS320TCI6486 DSP Host Port Interface (HPI) User's Guide. This guide
describes the host port interface (HPI) on the TMS320C6472/TMS320TCI6486 digital signal
processors (DSPs). The HPI enables an external host processor (host) to directly access the
internal or external memory of the DSP using a 16-bit (HPI16) interface.
SPRUEG4 TMS320C6472/TMS320TCI6486 DSP Telecom Serial Interface Port (TSIP) User's Guide.
This document describes the operation of the TMS320C6472/TMS320TCI6486 DSP
Telecom Serial Interface Port (TSIP).
SPRU725 TMS320C6472/TMS320TCI648x DSP General-Purpose Input/Output (GPIO) User’s
Guide. This document describes the general-purpose input/output (GPIO) peripheral in the
digital signal processors (DSPs) of the TMS320C6472/TMS320TCI648x DSP family.
SPRU818 TMS320C6472/TMS320TCI648x DSP 64-Bit Timer User’s Guide. This document provides
an overview of the 64-bit timer in the TMS320C6472/TMS320TCI648x DSP. The timer can
be configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a
watchdog timer.
SPRU727 TMS320C6472/TMS320TCI648x DSP Enhanced DMA (EDMA3) Controller User's Guide.
This document describes the Enhanced DMA (EDMA3) Controller in the
TMS320C6472/TMS320TCI648x DSP.
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