Datasheet

PRODUCTPREVIEW
imer x [6 thru 11](A)
imer x [6 thru 11](A)
imer x [6 thru 11](A)
imer x [6 thru 11](A)
Timer x [6 thru 11](A)
Timer x [0-5]
(B)
EMAC1
SS-SMII
RGMII
Serial
RapidIO
DDR2
Memory
Controller
Power-Down
Logic
DSP Subsystem 0
PLL1 and
PLL1 Controller
Boot Configuration
UTOPIA (16/8)
I2C
GPIO16
16
TSIP0
Shared L2 Controller
TSIP1
HPI (16-bit)
DDR2
SDRAM
32
Timer x [6-11]
(Shared)
(A)(B)
PLL3 and
PLL3
Controller
EDMA 3.0
System
(C)
Power Control
C64x+ DSP Core
Data Path B
B Register File
Instruction Fetch
Data Path A
A Register File
.L1
.S1
.M1
xx
xx
.D1
Internal DMA (IDMA)
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
Instruction
Decode
16-/32-bit
Instruction Dispatch
Control Registers
In-Circuit Emulation
SPLOOP Buffer
L1D Memory Controller (Memory Protect/Bandwidth Mgmt)
Interrupt and Exception Controller
EMAC0
32K Bytes
L1P SRAM/Cache
Direct-Mapped
TSIP2
PLL2 and
PLL2 Controller
L2 SRAM/Cache
608K Bytes
4-Way Set Assoc.
A31-A16
A15-A0
B31-B16
B15-B0
SS-SMII
GMII
MII
RGMII
RMII
32K-Bytes Total
L1D SRAM/Cache 2-Way
Set-Associative
M
e
g
a
m
o
d
u
l
e
SL2 RAM 768K-Bytes
Boot ROM
L2 Memory Controller
(Memory Protect/
Bandwidth Mgmt)
Switched Central Resource (SCR)
MDIO
RMII
.D2
.M2
xx
xx
.S2
.L2
DSP Subsystem 1
DSP Subsystem 2
DSP Subsystem 3
DSP Subsystem 4
DSP Subsystem 5
A. Timers 6-11 are shared.
B. Each of the Timer peripherals are configurable as either one 64-bit general-purpose timer two 32-bit general-purpose timers
a watchdog timer.
C. System consists of Test, Emulation, Power Down, and Interrupt Controller.
or or
TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
1.3 Functional Block Diagram
Figure 1-2 shows the functional block diagram of the C6472 device.
Figure 1-2. C6472 Functional Block Diagram
4 Features Copyright © 2009–2011, Texas Instruments Incorporated
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