Datasheet

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TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
Table 2-5. Terminal Functions (continued)
SIGNAL
TYPE
(1)
IPD/IPU
(2) (3)
DESCRIPTION
NAME NO.
UXDATA0 G25
UXDATA1 F26
UXDATA2 E27
UXDATA3 H25
UXDATA4 G26
UXDATA5 F27
UXDATA6 E28
UXDATA7 E29
UTOPIA 16-bit transmit data bus (also supports 8-bit mode on
O/Z IPD
pins [7:0])
UXDATA8 J25
UXDATA9 H26
UXDATA10 G27
UXDATA11 F28
UXDATA12 G28
UXDATA13 H28
UXDATA14 J27
UXDATA15 H29
UTOPIA transmit interface enable input signal. Asserted by the
Master ATM Controller to indicate that the UTOPIA slave should
UXENB AA26 I IPU
transmit one or more cells on the UXDATA bus with UXSOC
active on the first data cycle.
Transmit start-of-cell signal. This signal is output by the UTOPIA
Slave on the rising edge of the UXCLK, indicating that the first
UXSOC F29 O/Z IPD
valid byte of the cell is available on the 16-bit Transmit Data Bus
(UXDATA[15:0]).
MANAGEMENT DATA INPUT/OUTPUT (MDIO)
GMDIO MDIO serial data input/output. Only active if MACSEL0[2:0] is any
AH10 I/O/Z IPU
value but 011 (RGMII).
GMDCLK MDIO serial clock output. Only active if MACSEL0[2:0] is any
AG9 O/Z IPU
value but 011 (RGMII).
RGMDIO MDIO serial data input/output. Only active if MACSEL0[2:0] = 011
AG18 I/O
(RGMII).
RGMDCLK MDIO serial clock output. Only active if MACSEL0[2:0] = 011
AF18 O
(RGMII).
ETHERNET MAC (EMAC0 and EMAC1) (MII0/GMII0/RMII[1:0]/S3MII[1:0])
EMAC Receive Data 0 (MRXD0) for MII0 [default], GMII0 and
MRXD00/RMRXD00/SRXD0 AH11 I IPU RMII0 or Receive Data (RXD) for S3MII0. Pin function defined by
MACSEL0[2:0] (see Table 3-1).
EMAC Receive Data 1 (MRXD1) for MII0 [default], GMII0 and
MRXD01/RMRXD01/SRXSYNC0 AG12 I IPU RMII0 or Receive Sync (RXSYNC) for S3MII0. Pin function
defined by MACSEL0[2:0] (see Table 3-1).
EMAC Receive Data 2 (MRXD2) for MII0 [default] and GMII0 or
MRXD02/SRXD1 AJ11 I IPU Receive Data (RXD) for S3MII1. Pin function defined by
MACSEL0[2:0] and MACSEL1[1:0] (see Table 3-1).
EMAC Receive Data 3 (MRXD3) for MII0 [default] and GMII0 or
MRXD03/SRXSYNC1 AJ10 I IPU Receive Sync (RXSYNC) for S3MII1. Pin function defined by
MACSEL0[2:0] and MACSEL1[1:0] (see Table 3-1).
EMAC Receive Data 4 (MRXD4) for GMII0 or Receive Data 0
MRXD04/RMRXD10 AH9 I IPU (RXD0) for RMII1. Pin function defined by MACSEL0[2:0] and
MACSEL1[1:0] (see Table 3-1).
EMAC Receive Data 5 (MRXD5) for GMII0 or Receive Data 1
MRXD05/RMRXD11 AG7 I IPU (RXD1) for RMII1. Pin function defined by MACSEL0[2:0] and
MACSEL1[1:0] (see Table 3-1).
34 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated
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