Datasheet

PRODUCTPREVIEW
TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
Table 2-5. Terminal Functions (continued)
SIGNAL
TYPE
(1)
IPD/IPU
(2) (3)
DESCRIPTION
NAME NO.
UNIVERSAL TEST AND OPERATIONS PHY INTERFACE FOR ASYNCHRONOUS TRANSFER MODE (ATM) [UTOPIA]
Source clock for UTOPIA receive driven by Master ATM
URCLK J29 I IPD
Controller.
Receive cell available status output signal from UTOPIA Slave.
0 indicates NO space is available to receive a cell from Master
URCLAV J28 O/Z IPD ATM Controller.
1 indicates space is available to receive a cell from Master ATM
Controller.
URADDR0 Y29
URADDR1 Y28
URADDR2 Y27 I IPD UTOPIA receive address bus
URADDR3 Y26
URADDR4 Y25
URDATA0 AA29
URDATA1 AA28
URDATA2 AA27
URDATA3 AB27
URDATA4 AB26
URDATA5 AB25
URDATA6 AC29
URDATA7 AC28
UTOPIA 16-bit receive data bus (also supports 8-bit mode on pins
I IPD
[7:0])
URDATA8 AC27
URDATA9 AC26
URDATA10 AC25
URDATA11 AD29
URDATA12 AD28
URDATA13 AD27
URDATA14 AF29
URDATA15 AD26
UTOPIA receive interface enable input signal. Asserted by the
Master ATM Controller to indicate to the UTOPIA slave to receive
URENB AE27 I IPU
one or more cells on the URDATA bus with URSOC active on the
first data cycle.
Receive start-of-cell signal. This signal is output by the Master
ATM Controller to indicate to the UTOPIA Slave that the first valid
URSOC AA25 I IPD
byte of the cell is available to sample on the 16-bit Receive Data
Bus (URDATA[15:0]).
Source clock for UTOPIA transmit driven by Master ATM
UXCLK J26 I IPD
Controller.
Transmit cell available status output signal from UTOPIA Slave.
UXCLAV H27 O/Z IPD 0 indicates a complete cell is NOT available for transmit.
1 indicates a complete cell is available for transmit.
UXADDR0 W29
UXADDR1 W28
UXADDR2 W27 I IPD UTOPIA transmit address bus
UXADDR3 W26
UXADDR4 W25
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