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TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
Table 2-5. Terminal Functions (continued)
SIGNAL
TYPE
(1)
IPD/IPU
(2) (3)
DESCRIPTION
NAME NO.
GP06/BOOTMODE0 L5 I/O/Z IPU
General-purpose input/output pin [9:6] multiplexed with
GP07/BOOTMODE1 L4 I/O/Z IPU
BOOTMODE selection pin [3:0] (for details, see Table 3-1 and
GP08/BOOTMODE2 K3 I/O/Z IPU
Section 2.4).
GP09/BOOTMODE3 K4 I/O/Z IPU
GP10/CFGGP0 M2 I/O/Z IPD
GP11/CFGGP1 N3 I/O/Z IPD
General-purpose input/output pin [14:10] multiplexed with
GP12/CFGGP2 M4 I/O/Z IPD
configuration selection pin [4:0].
GP13/CFGGP3 L1 I/O/Z IPD
GP14/CFGGP4 L2 I/O/Z IPD
General-purpose input/output pin 15 multiplexed with
SYSCLKOUT enable.
GP15/SYSCLKOUTEN L3 I/O/Z IPD
0 = SYSCLKOUT is disabled (default)
1 = SYSCLKOUT is enabled
DDR2 MEMORY CONTROLLER
BSDDQM3 C16 O/Z DDR2 Memory Controller byte-enable controls
• Decoded from the low-order address bits. The number of
BSDDQM2 B15 O/Z
address bits or byte enables used depends on the width of
BSDDQM1 G4 O/Z
external memory.
• Byte-write enables for most types of memory.
BSDDQM0 A3 O/Z
• Can be directly connected to SDRAM read and write mask
signal (SDQM).
BCS1 E9 O/Z DDR2 Memory Controller memory space enable. When the DDR2
Memory Controller is enabled, it first sets these pins low. Then as
accesses occur to the DDR2 memory, only the chip select
BCS0 A4 O/Z
corresponding to the accessed DDR2 memory is low.
BBA2 A6 O/Z
BBA1 B6 O/Z DDR2 Memory Controller bank address control
BBA0 C7 O/Z
BEA00 B12
BEA01 A12
BEA02 A11
BEA03 B11
BEA04 C11
BEA05 D11
BEA06 A9
O/Z DDR2 Memory Controller address bus
BEA07 C10
BEA08 D10
BEA09 C9
BEA10 B8
BEA11 A7
BEA12 B7
BEA13 D9
BECLKOUTP C8 O/Z
DDR2 Memory Controller output clock (CLKIN3 frequency × 10) -
differential output
BECLKOUTN D8 O/Z
30 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated
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