Datasheet

PRODUCTPREVIEW
TelecomSerialInterfacePort
TX0[7:0]
TR0[7:0]
TSIP2
TX2[7:0]
TR2[7:0]
TX1[7:0]
TR1[7:0]
TSIP0
TSIP1
Transmit
Receive
Control
Clock
Transmit
Receive
Control
Clock
Transmit
Receive
Control
Clock
8
8
8
8
FSA0
FSB0
CLKA0
CLKB0
FSA2
FSB2
8
8
FSA1
FSB1
CLKA1
CLKB1
CLKA2
CLKB2
TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
Figure 2-12. TSIP[2:0] Peripheral Signals
28 Device Overview Copyright © 2009–2011, Texas Instruments Incorporated
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