Datasheet

PRODUCTPREVIEW
BECLKOUTP
BED[31:0]
BCS0
BEA[13:0]
Data
MemoryMap
SpaceSelect
Address
ByteEnables
32
14
External
MemoryI/F
Control
DDR2MemoryController(32-bitDataBus)
BSDCAS
BSDCKE
BECLKOUTN
BSDDQSP[3:0]
BSDRAS
BSDWE
BSDDQSN[3:0]
Bank Address
BBA[2:0]
BSDDQGATE[3:0]
BSDDQM3
BSDDQM2
BSDDQM1
BSDDQM0
BCS1
TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
Figure 2-8. DDR2 Memory Controller Peripheral Signals
Copyright © 2009–2011, Texas Instruments Incorporated Device Overview 25
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