Datasheet

PRODUCTPREVIEW
TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
7.18 Serial RapidIO (SRIO) Port
The SRIO ports on the C6472 device are high-performance, low-pin-count interconnects aimed for
embedded markets. The use of the RapidIO interconnect in a system board design can create a
homogeneous interconnect environment providing simple, high-throughput connectivity and control among
the devices. RapidIO is based on the memory and device addressing concepts of processor buses where
the transaction processing is managed completely by hardware. This enables the RapidIO interconnect to
lower the system cost by providing low latency, reduced overhead, packet data processing and high
system bandwidth. The RapidIO interconnect offers very-low-pin count interfaces with scalable system
bandwidth. The C6472 device contains two independent 1x lanes. The lanes can operate at 1.25, 2.5, or
3.135 Gbps.
The PHY part of the SRIO consists of the physical layer and includes the input and output buffers (each
serial link consists of a differential pair), the 8-bit/10-bit encoder/decoder, the PLL clock recovery, and the
parallel-to-serial/serial-to-parallel converters (SERDES).
The transmitter supports programmable output levels and de-emphasis settings. The receiver has
equalization that can be converged automatically or programmed statically.
7.18.1 Serial RapidIO Device-Specific Information
The approach to specifying interface timing for the SRIO Port is different than on other interfaces such as
HPI. For these other interfaces the device timing was specified in terms of data manual specifications and
I/O buffer information specification (IBIS) models.
For the C6472 SRIO Port, Texas Instruments (TI) provides a printed circuit board (PCB) solution showing
two DSPs connected via a 1x SRIO link directly to the user. TI has performed the simulation and system
characterization to ensure all SRIO interface timings in this solution are met. The complete SRIO system
solution is documented in the TMS320C6472/TMS320TCI6486 Serial RapidIO Implementation Guidelines
application report (literature number SPRAAT9).
TI only supports designs that follow the board design guidelines outlined in the SPRAAT9
application report.
The Serial RapidIO peripheral is a master peripheral in the C6472 DSP. It conforms to the RapidIO™
Interconnect Specification, Part VI: Physical Layer 1x/4x LP-Serial Specification, Revision 1.2. For more
information from an application perspective, see the TMS320C6472/TMS320TCI648x Serial RapidIO
(SRIO) User's Guide (literature number SPRUE13).
7.18.2 SRIO Peripheral Register Descriptions
Table 7-150. RapidIO Control Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
02D0 0000 PID Peripheral Identification Register
02D0 0004 PCR Peripheral Control Register
02D0 0008 - 02D0 001C - Reserved
02D0 0020 PER_SET_CNTL Peripheral Settings Control Register
02D0 0024 - 02D0 002C - Reserved
02D0 0030 GBL_EN Peripheral Global Enable Register
02D0 0034 GBL_EN_STAT Peripheral Global Enable Status
02D0 0038 BLK0_EN Block Enable 0
02D0 003C BLK0_EN_STAT Block Enable Status 0
02D0 0040 BLK1_EN Block Enable 1
02D0 0044 BLK1_EN_STAT Block Enable Status 1
02D0 0048 BLK2_EN Block Enable 2
02D0 004C BLK2_EN_STAT Block Enable Status 2
248 C64x+ Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s) :TMS320C6472