Datasheet

PRODUCTPREVIEW
P46
N
20
UXCLK
(input)
UXDATA[15:0]
(output)
UXADDR[4:0]
(input)
UXCLAV
(output)
UXENB
(input)
UXSOC
(output)
P45
P47
P48
H1
N
1Fh
N N+1
N
19
22 21
17
24
28
23
27
26
25
16
1Fh 1Fh
18
TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
Table 7-148. Timing Requirements for UTOPIA Slave Transmit Cycles
(see Figure 7-64)
500/625/700
NO. UNIT
MIN MAX
16 t
su(UXADDR-UXCLKH)
Setup time, UXADDR valid before UXCLK high 4 ns
17 t
h(UXCLKH-UXADDR)
Hold time, UXADDR valid after UXCLK high 1 ns
18 t
su(UXENB-UXCLKH)
Setup time, UXENB valid before UXCLK high 4 ns
19 t
h(UXCLKH-UXENB)
Hold time, UXENB valid after UXCLK high 1 ns
Table 7-149. Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave
Transmit Cycles
(see Figure 7-64)
500/625/700
NO. PARAMETER UNIT
MIN MAX
20
(1)
t
d(UXCLKH-UXDATAV)
Delay time, UXCLK high to UXDATA valid 2 10 ns
21
(1)
t
en(UXCLKH-UXDATA)
Enable time, UXCLK high to UXDATA driven 2 10 ns
22
(2) (3)
t
dis(UXCLKH-UXDATAZ)
Disable time, UXCLK high to UXDATA high-impedance state 2 10 ns
23
(1)
t
d(UXCLKH-UXCLAV)
Delay time, UXCLK high to UXCLAV driven low 2 10 ns
24
(1)
t
en(UXCLKH-UXCLAV)
Enable time, UXCLK high to UXCLAV driven high 2 10 ns
25
(2) (3)
t
dis(UXCLKL-UXCLAVZ)
Disable time, UXCLK low to UXCLAV high-impedance state 2 10 ns
26
(1)
t
d(UXCLKH-UXSOCV)
Delay time, UXCLK high to UXSOC valid 2 10 ns
27
(1)
t
en(UXCLKH-UXSOC)
Enable time, UXCLK high to UXSOC driven 2 10 ns
28
(2) (3)
t
dis(UXCLKH-UXSOCZ)
Disable time, UXCLK high to UXSOC high-impedance state 2 10 ns
(1) MAX delay time and enable time increases to 12.5 ns at 20 pF and 14 ns at 30 pF, specified by design.
(2) Specifed by design for MIN values.
(3) Specifed by design for MAX values.
Figure 7-64. UTOPIA Slave Transmit
Copyright © 2009–2011, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 247
Submit Documentation Feedback
Product Folder Link(s) :TMS320C6472