Datasheet

PRODUCTPREVIEW
UXCLK
URCLK
(inputs)
1
4 4
2
3
TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
7.17.3 UTOPIA Electrical Data/Timing
Table 7-145. Timing Requirements for UTOPIA Receive/Transmit Clock (UCLK)
(1)
(see Figure 7-62)
500/625/700
NO. UNIT
MIN MAX
1 t
c(UCLK)
UXCLK or URCLK cycle time 20 ns
2 t
w(UCLKL)
UXCLK or URCLK pulse duration low 0.4t
c(URCLK)
0.6t
c(URCLK)
ns
3 t
w(UCLKH)
UXCLK or URCLK pulse duration high 0.4t
c(URCLK)
0.6t
c(URCLK)
ns
4 t
t(UCLK)
Transition time, UXCLK or URCLK (high to low or low to high) 2 ns
(1) UCLK = UXCLK or URCLK.
Figure 7-62. UTOPIA Clock
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