Datasheet
PRODUCTPREVIEW
MDCLK
MDIO
(input)
1
4
5
2
2
3
1
MDCLK
MDIO
(output)
7
TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011
www.ti.com
7.15.5.3 MDIO Electrical Data/Timing
Table 7-125. Timing Requirements for MDIO Input
(see Figure 7-58)
500/625/700
NO. UNIT
MIN MAX
1 t
c(MDCLK)
Cycle time, MDCLK 400 ns
t
w(MDCLKH)
Pulse duration, MDCLK high 180 ns
2
t
w(MDCLKL)
Pulse duration, MDCLK low 180 ns
3 t
t(MDCLK)
Transition time, MDCLK 5 ns
4 t
su(MDIO-MDCLKH)
Setup time, MDIO data input valid before MDCLK high 25 ns
5 t
h(MDCLKH-MDIO)
Hold time, MDIO data input valid after MDCLK high 10 ns
Figure 7-58. MDIO Input Timing
Table 7-126. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 7-59)
500/625/700
NO. PARAMETER UNIT
MIN MAX
7 t
d(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output valid 100 ns
Figure 7-59. MDIO Output Timing
236 C64x+ Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated
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