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RGCLK
2
3
4
4
1
TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
7.15.4.3 EMAC RGMII Electrical Data/Timing
An extra clock signal, RGREFCLK, running at 125 MHz is included as a convenience to the user. Note
that this reference clock is not a free-running clock. This should only be used by an external device if it
does not expect a valid clock during device reset.
Table 7-119. Switching Characteristics Over Recommended Operating Conditions for EMAC RGREFCLK -
RGMII Operation
(see Figure 7-53)
500/625/700
NO. PARAMETER UNIT
MIN TYP MAX
1 t
c(RGFCLK)
Cycle time, RGREFCLK 8 ns
2 t
w(RGFCLKH)
Pulse duration, RGREFCLK high 0.45 * t
c(RGFCLK)
0.55 * t
c(RGFCLK)
ns
3 t
w(RGFCLKL)
Pulse duration, RGREFCLK low 0.45 * t
c(RGFCLK)
0.55 * t
c(RGFCLK)
ns
4 t
t(RGFCLK)
Transition time, RGREFCLK 0.5 ns
Figure 7-53. RGMII Reference Clock (Output)
Copyright © 2009–2011, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 231
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