Datasheet

PRODUCTPREVIEW
TRST
IEEEStandard
1149.1
(JTAG)
Emulation
Resetand
Interrupts
Control/Status
TDI
TDO
TMS
TCLK
Clock/PLL1
and
PLL Controller
EMU0
EMU1
CLKIN1
SYSCLKOUT
EMU14
EMU15
EMU16
EMU17
EMU18
·
·
·
CLKIN2
Clock/PLL2
(EMAC)
Clock/PLL3
(DDR2)
CLKIN3
RESET
RESETSTAT
POR
LRESETNMIEN
CORSEL[2:0]
LRESET
NMI
HOUT
DDREN
RIOEN
MACSEL0[2:0]
MACSEL1[1:0]
LENDIAN
Peripheral
Enable/Disable
BOOTACTIVE
TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
2.6 Signal Groups Description
Figure 2-6. CPU and Peripheral Signals
Copyright © 2009–2011, Texas Instruments Incorporated Device Overview 23
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