Datasheet

PRODUCTPREVIEW
[G]MTCLK
2 3
1
4
4
MRCLK (input)
1
2
MRXD3-MRXD0,
MRXDV, MRXER (inputs)
TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
Figure 7-49. [G]MTCLK Timing
Table 7-112. Timing Requirements for EMAC MII and GMII Receive 10/100 Mbit/s
(see Figure 7-50)
500/625/700
NO. PARAMETER 10/100 Mbps UNIT
MIN MAX
t
su(GMII_MRXD)
Setup time, GMII_MRXD to GMII_MRCLK rising edge 8
1 t
su(GMII_MRXDV)
Setup time, GMII_MRXDV to GMII_MRCLK rising edge 8 ns
t
su(GMII_MRXER)
Setup time, GMII_MRXER to GMII_MRCLK rising edge 8
t
h(GMII_MRXD)
Hold time, GMII_MRXD valid after GMII_RCLK rising edge 8
2 t
h(GMII_MRXDV)
Hold time, GMII_MRXDV valid after GMII_RCLK rising edge 8 ns
t
h(GMII_MRXER)
Hold time, GMII_MRXDV valid after GMII_RCLK rising edge 8
Table 7-113. Timing Requirements for EMAC MII and GMII Receive 1000 Mbit/s
(see Figure 7-50)
500/625/700
NO. PARAMETER 1000 Mbps UNIT
MIN MAX
t
su(GMII_G_MRXD)
Setup time, GMII_MRXD to GMII_MRCLK rising edge 2.5
1 t
su(GMII_G_MRXDV)
Setup time, GMII_MRXDV to GMII_MRCLK rising edge 2.5 ns
t
su(GMII_G_MRXER)
Setup time, GMII_MRXER to GMII_MRCLK rising edge 2.5
t
h(GMII_G_MRXD)
Hold time, GMII_MRXD valid after GMII_RCLK rising edge 0.2
2 t
h(GMII_G_MRXDV)
Hold time, GMII_MRXDV valid after GMII_RCLK rising edge 0.2 ns
t
h(GMII_G_MRXER)
Hold time, GMII_MRXDV valid after GMII_RCLK rising edge 0.2
Figure 7-50. Input Timing
228 C64x+ Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated
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