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TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
Table 7-103. EMAC1 Control Registers (continued)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
02CC 00B4 MACINTSTATMASKED MAC Interrupt Status (Masked) Register
02CC 00B8 MACINTMASKSET MAC Interrupt Mask Set Register
02CC 00BC MACINTMASKCLEAR MAC Interrupt Mask Clear Register
02CC 00C0 - 02CC 00FC - Reserved
02CC 0100 RXMBPENABLE Receive Multicast/Broadcast/Promiscuous Channel Enable Register
02CC 0104 RXUNICASTSET Receive Unicast Enable Set Register
02CC 0108 RXUNICASTCLEAR Receive Unicast Clear Register
02CC 010C RXMAXLEN Receive Maximum Length Register
02CC 0110 RXBUFFEROFFSET Receive Buffer Offset Register
02CC 0114 RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register
02CC 0118 - 02CC 011C - Reserved
02CC 0120 RX0FLOWTHRESH Receive Channel 0 Flow Control Threshold Register
02CC 0124 RX1FLOWTHRESH Receive Channel 1 Flow Control Threshold Register
02CC 0128 RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register
02CC 012C RX3FLOWTHRESH Receive Channel 3 Flow Control Threshold Register
02CC 0130 RX4FLOWTHRESH Receive Channel 4 Flow Control Threshold Register
02CC 0134 RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register
02CC 0138 RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register
02CC 013C RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register
02CC 0140 RX0FREEBUFFER Receive Channel 0 Free Buffer Count Register
02CC 0144 RX1FREEBUFFER Receive Channel 1 Free Buffer Count Register
02CC 0148 RX2FREEBUFFER Receive Channel 2 Free Buffer Count Register
02CC 014C RX3FREEBUFFER Receive Channel 3 Free Buffer Count Register
02CC 0150 RX4FREEBUFFER Receive Channel 4 Free Buffer Count Register
02CC 0154 RX5FREEBUFFER Receive Channel 5 Free Buffer Count Register
02CC 0158 RX6FREEBUFFER Receive Channel 6 Free Buffer Count Register
02CC 015C RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register
02CC 0160 MACCONTROL MAC Control Register
02CC 0164 MACSTATUS MAC Status Register
02CC 0168 EMCONTROL Emulation Control Register
02CC 016C FIFOCONTROL FIFO Control Register (Transmit and Receive)
02CC 0170 MACCONFIG MAC Configuration Register
02CC 0174 SOFTRESET Soft Reset Register
02CC 0178 - 02CC 01CC - Reserved
02CC 01D0 MACSRCADDRLO MAC Source Address Low Bytes Register (Lower 16-bits)
02CC 01D4 MACSRCADDRHI MAC Source Address High Bytes Register (Upper 16-bits)
02CC 01D8 MACHASH1 MAC Hash Address Register 1
02CC 01DC MACHASH2 MAC Hash Address Register 2
02CC 01E0 BOFFTEST Back Off Test Register
02CC 01E4 TPACETEST Transmit Pacing Algorithm Test Register
02CC 01E8 RXPAUSE Receive Pause Timer Register
02CC 01EC TXPAUSE Transmit Pause Timer Register
02CC 01F0 - 02CC 01FC - Reserved
02CC 0200 - 02CC 02FC (see Table 7-102) EMAC Statistics Registers
02CC 0300 - 02CC 04FC - Reserved
MAC Address Low Bytes Register (Used in Receive Address
02CC 0500 MACADDRLO
Matching)
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