Datasheet

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TMS320C6472
SPRS612GJUNE 2009 REVISED JULY 2011
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Table 7-100. EMAC/MDIO Multiplexed Pins (MII, GMII0, RMII, and S3MII Modes) (continued)
PIN
SIGNAL NAME MII0 GMII0 RMII0 RMII1 S3MII0 S3MII1
NUMBER
AE7 MTXD04/RMTXD10/STXCLK1 MTXD04 RMTXD10 STXCLK1
AJ7 MTXD05/RMTXD11 MTXD05 RMTXD11
AE11 MTXD06/RMTXEN1 MTXD06 RMTXEN1
AG11 MTXD07/STXCLK0 MTXD07 STXCLK0
AF11 MTXEN0/RMTXEN0 MTXEN0 MTXEN0 RMTXEN0
AE8 MCOL0 MCOL0 MCOL0
AH10 GMDIO GMDIO GMDIO
AG9 GMDCLK GMDCLK GMDCLK
The on-chip PLL2 and PLL2 Controller generate all the internal clocks to the EMAC module. When
enabled, the input clock to the PLL2 Controller (CLKIN2) must have a 25-MHz frequency. For more
information, see Section 7.9, PLL2 and PLL2 Controller, of this document.
218 C64x+ Peripheral Information and Electrical Specifications Copyright © 20092011, Texas Instruments Incorporated
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