Datasheet

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TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
7.15.1 EMAC Device-Specific Information
Interface Modes
The EMAC module on the TMS320C6472 device supports five interface modes: Media Independent
Interface (MII), Reduced Media Independent Interface (RMII), Source Synchronous Serial Media
Independent Interface (S3MII), Gigabit Media Independent Interface (GMII), and Reduced Gigabit Media
Independent Interface (RGMII). The MII and GMII interface modes are defined in the IEEE 802.3-2002
standard.
The RGMII mode of the EMAC conforms to the Reduced Gigabit Media Independent Interface (RGMII)
Specification (version 2.0). The RGMII mode implements the same functionality as the GMII mode, but
with a reduced number of pins. Data and control information is transmitted and received using both edges
of the transmit and receive clocks (TXC and RXC).
Note: The EMAC internally delays the transmit clock (TXC) with respect to the transmit data and control
pins. Therefore, the EMAC conforms to the RGMII-ID operation of the RGMII specification. However, the
EMAC does not delay the receive clock (RXC); this signal must be delayed with respect to the receive
data and control pins outside of the DSP.
The RMII mode of the EMAC conforms to the RMII Specification (revision 1.2), as written by the RMII
Consortium, except for the half-duplex mode, which is not supported. As the name implies, the Reduced
Media Independent Interface (RMII) mode is a reduced pin count version of the MII mode.
The S3MII mode of the EMAC conforms to the Serial-MII Specification (revision 2.1).
Interface Mode Select
The EMAC uses the same pins for the (G)MII, RMII, and S3MII modes. Standalone pins are included for
the RGMII mode, due to specific voltage requirements. Only one mode can be used at a time for each
EMAC port. The mode used is selected at device reset based on the MACSEL0[2:0] and MACSEL1[1:0]
configuration pins (for more detailed information, see Section 3, Device Configuration, of this document).
Table 7-100 shows all the multiplexed pins used in the (G)MII, RMII, and S3MII modes on EMAC. For a
detailed description of these pin functions, see Section 2.7, Terminal Functions.
Table 7-100. EMAC/MDIO Multiplexed Pins (MII, GMII0, RMII, and S3MII Modes)
PIN
SIGNAL NAME MII0 GMII0 RMII0 RMII1 S3MII0 S3MII1
NUMBER
AH11 MRXD00/RMRXD00/SRXD0 MRXD00 MRXD00 RMRXD00 SRXD0
AG12 MRXD01/RMRXD01/SRXSYNC0 MRXD01 MRXD01 RMRXD01 SRXSYNC0
AJ11 MRXD02/SRXD1 MRXD02 MRXD02 SRXD1
AG10 MRCLK0/SRXCLK1 MRCLK0 MRCLK0 SRXCLK1
AJ10 MRXD03/SRXSYNC1 MRXD03 MRXD03 SRXSYNC1
AH9 MRXD04/RMRXD10 MRXD04 RMRXD10
AG7 MRXD05/RMRXD11 MRXD05 RMRXD11
AJ13 MRXD06/RMRXER1 MRXD06 RMRXER1
AJ6 MRXD07 MRXD07
AE12 MRXDV0/RMCRSDV1 MRXDV0 MRXDV0 RMCRSDV1
AF12 MRXER0/RMRXER0/SRXCLK0 MRXER0 MRXER0 RMRXER0 SRXCLK0
AF10 MCRS0/RMCRSDV0 MCRS0 MCRS0 RMCRSDV0
AG6 GMTCLK0/REFCLK1/SREFCLK1 GMTCLK0 REFCLK1 SREFCLK1
AJ9 MTCLK0/REFCLK0/SREFCLK0 MTCLK0 MTCLK0 REFCLK0 SREFCLK0
AF8 MTXD00/RMTXD00/STXD0 MTXD00 MTXD00 RMTXD00 STXD0
AH7 MTXD01/RMTXD01/STXSYNC0 MTXD01 MTXD01 RMTXD01 STXSYNC0
AG8 MTXD02/STXD1 MTXD02 MTXD02 STXD1
AF9 MTXD03/STXSYNC1 MTXD03 MTXD03 STXSYNC1
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