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ts127-2
ts127-0
ts127-1
ts000-7 ts000-6 ts000-1ts000-3ts000-5 ts000-4 ts000-2 ts000-0
16
15
11 13
12
CLKA/B
FSA/B
TRn
(A)
TXn
(A)
17
18
19 20
ts127-2
ts000-3ts000-7
ts127-1
ts127-0
ts000-5ts000-6 ts000-4 ts000-0ts000-2 ts000-1
TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
Table 7-99. Timing Requirements for TSIP 1X Mode
(1)
(see Figure 7-46)
500/625/700
NO. UNIT
MIN MAX
11 t
c(CLK)
Cycle time, CLK rising edge to next CLK rising edge 122.1
(2)
ns
12 t
w(CLKL)
Pulse duration, CLK low 0.4 t
c(clk)
ns
13 t
w(CLKH)
Pulse duration, CLK high 0.4 t
c(clk)
ns
14 t
t(CLK)
Transition time, CLK high to low or CLK low to high 2 ns
15 t
su(FS-CLK)
Setup time, f
s
valid before rising CLK 5 ns
16 t
h(CLK-FS)
Hold time, f
s
valid after rising CLK 5 ns
17 t
su(TR-CLK)
Setup time, t
r
valid before falling CLK 5 ns
18 t
h(CLK-TR)
Hold time, t
r
valid before falling CLK 5 ns
19 t
d(CLKH-TX)
Delay time, CLK high to TX valid (1024
(2)
clock cycles plus) 1 12 ns
20 t
dis(CLKH-TXZ)
Disable time, CLK high to TX tristate 1 12 ns
(1) Polarities of XMTFSYNCP = 0b, XMTFCLKP = 0, XMTDCLKP = 0b, RCVFSYNCP = 0, RCVFCLKP = 0, RCVDCLKP = 1. If the polarity
of any of the signals is inverted, then the timing references of that signal are also inverted.
(2) Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 61 ns and 30.5 ns, respectively.
A. Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through
255 and 32.768 Mbps links have timeslots numbered 0 through 511. The data timing shown relative to the clock and
frame sync signals would require a RCVDATD=1023 and a XMTDATD=1023.
Figure 7-46. TSIP 1x Timing Diagram
Copyright © 2009–2011, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 215
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