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TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
Table 7-67. DMATCU Receive Channels 0-5 Registers (continued)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0250 1908 DRCH_AFSIZE4 Receive Channel 4 Frame Size Register A
0250 190C DRCH_AFCNT4 Receive Channel 4 Frame Count Register A
0250 1910 - 0250 191C - Reserved
0250 1920 DRCH_BBASE4 Receive Channel 4 Memory Base Address Register B
0250 1924 DRCH_BFALLOC4 Receive Channel 4 Frame Allocation Register B
0250 1928 DRCH _BFSIZE4 Receive Channel 4 Frame Size Register B
0250 192C DRCH _BFCNT4 Receive Channel 4 Frame Count Register B
0250 1930 - 0250 193C - Reserved
0250 1940 DRCH_ABASE5 Receive Channel 5 Memory Base Address Register A
0250 1944 DRCH_AFALLOC5 Receive Channel 5 Frame Allocation Register A
0250 1948 DRCH_AFSIZE5 Receive Channel 5 Frame Size Register A
0250 194C DRCH_AFCNT5 Receive Channel 5 Frame Count Register A
0250 1950 - 0250 195C - Reserved
0250 1960 DRCH_BBASE5 Receive Channel 5 Memory Base Address Register B
0250 1964 DRCH_BFALLOC5 Receive Channel 5 Frame Allocation Register B
0250 1968 DRCH _BFSIZE5 Receive Channel 5 Frame Size Register B
0250 196C DRCH _BFCNT5 Receive Channel 5 Frame Count Register B
0250 1970 - 0250 197C - Reserved
Table 7-68. TDMU Channel Bitmaps
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0250 8000 - 0250 80FC XBM_XBMA0 Transmit Channel 0 Bitmap A
0250 8100 - 0250 81FC XBM_XBMB0 Transmit Channel 0 Bitmap B
0250 8200 - 0250 82FC XBM_XBMA1 Transmit Channel 1 Bitmap A
0250 8300 - 0250 83FC XBM_XBMB1 Transmit Channel 1 Bitmap B
0250 8400 - 0250 84FC XBM_XBMA2 Transmit Channel 2 Bitmap A
0250 8500 - 0250 85FC XBM_XBMB2 Transmit Channel 2 Bitmap B
0250 8600 - 0250 86FC XBM_XBMA3 Transmit Channel 3 Bitmap A
0250 8700 - 0250 87FC XBM_XBMB3 Transmit Channel 3 Bitmap B
0250 8800 - 0250 88FC XBM_XBMA4 Transmit Channel 4 Bitmap A
0250 8900 - 0250 89FC XBM_XBMB4 Transmit Channel 4 Bitmap B
0250 8A00 - 0250 8AFC XBM_XBMA5 Transmit Channel 5 Bitmap A
0250 8B00 - 0250 8BFC XBM_XBMB5 Transmit Channel 5 Bitmap B
0250 8C00 - 0250 BFFC - Reserved
0250 C000 - 0250 C0FC RBM_RBMA0 Receive Channel 0 Bitmap A
0250 C100 - 0250 C1FC RBM_RBMB0 Receive Channel 0 Bitmap B
0250 C200 - 0250 C2FC RBM_RBMA1 Receive Channel 1 Bitmap A
0250 C300 - 0250 C3FC RBM_RBMB1 Receive Channel 1 Bitmap B
0250 C400 - 0250 C4FC RBM_RBMA2 Receive Channel 2 Bitmap A
0250 C500 - 0250 C5FC RBM_RBMB2 Receive Channel 2 Bitmap B
0250 C600 - 0250 C6FC RBM_RBMA3 Receive Channel 3 Bitmap A
0250 C700 - 0250 C7FC RBM_RBMB3 Receive Channel 3 Bitmap B
0250 C800 - 0250 C8FC RBM_RBMA4 Receive Channel 4 Bitmap A
0250 C900 - 0250 C9FC RBM_RBMB4 Receive Channel 4 Bitmap B
0250 CA00 - 0250 CAFC RBM_RBMA5 Receive Channel 5 Bitmap A
0250 CB00 - 0250 CBFC RBM_RBMB5 Receive Channel 5 Bitmap B
0250 CC00 - 0250 FFFC - Reserved
196 C64x+ Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated
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