Datasheet

PRODUCTPREVIEW
TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
Table 7-55. Switching Characteristics Over Recommended Operating Conditions for
Host-Port Interface Cycles
(1)(2)(3)
(see Figure 7-41 through Figure 7-44)
500/625/700
NO. PARAMETER UNIT
MIN MAX
Case 1. HPIC or HPIA read 3 20
Case 2. HPID read with no
17 * M + 20
auto-increment
Delay time, HSTROBE low to
Case 3. HPID read with auto-increment
1 t
d(HSTBL-HDV)
ns
16 * M + 20
DSP data valid
and read FIFO initially empty
Case 4. HPID read with auto-increment
and data previously prefetched into the 3 20
read FIFO
2 t
dis(HSTBH-HDV)
Disable time, HD high-impedance from HSTROBE high 1 12 ns
3 t
en(HSTBL-HD)
Enable time, HD driven from HSTROBE low 2 20 ns
4 t
d(HSTBL-HRDYH)
Delay time, HSTROBE low to HRDY high 20 ns
5 t
d(HSTBH-HRDYH)
Delay time, HSTROBE high to HRDY high 20 ns
Case 1. HPID read with no
18 * M + 20
auto-increment
Delay time, HSTROBE low to
6 t
d(HSTBL-HRDYL)
ns
HRDY low
Case 2. HPID read with auto-increment
17 * M + 20
and read FIFO initially empty
7 t
d(HDV-HRDYL)
Delay time, HD valid to HRDY low 0 ns
Case 1. HPIA write 5 * M + 20
Delay time, HSTROBE high to
34 t
d(DSH-HRDYL)
ns
Case 2. HPID write with no
HRDY low
5 * M + 20
auto-increment
Delay time, HSTROBE low to HRDY low for HPIA write and FIFO not
35 t
d(HSTBL-HRDYL)
40 * M + 20 ns
empty
36 t
d(HASL-HRDYH)
Delay time, HAS low to HRDY high 20 ns
(1) M = HPI module clock period = 6 * CPU clock period or 12 ns at 500 MHz. (This duration will be much longer when PLL1 is in bypass
mode.)
(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(3) Maximum delays for 1 (cases 2 and 3), 6, 34, and 35 assume no conflict with SCR. The true maximum delay during application
execution is dependent on internal congestion delays. HRDY must be used to guarantee valid cycle completion.
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