Datasheet

PRODUCTPREVIEW
TMS320C6472
SPRS612GJUNE 2009 REVISED JULY 2011
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7.13.4 HPI Electrical Data/Timing
Table 7-54. Timing Requirements for Host-Port Interface Cycles
(1)(2)
(see Figure 7-41 through Figure 7-44)
500/625/700
NO. UNIT
MIN MAX
9 t
su(HASL-HSTBL)
Setup time, HAS low before HSTROBE low 5 ns
10 t
h(HSTBL-HASL)
Hold time, HAS low after HSTROBE low 2 ns
11 t
su(SELV-HASL)
Setup time, select signals
(3)
valid before HAS low 5 ns
12 t
h(HASL-SELV)
Hold time, select signals
(3)
valid after HAS low 5 ns
13 t
w(HSTBL)
Pulse duration, HSTROBE low 2M ns
14 t
w(HSTBH)
Pulse duration, HSTROBE high between consecutive accesses 2M ns
15 t
su(SELV-HSTBL)
Setup time, select signals
(3)
valid before HSTROBE low 5 ns
16 t
h(HSTBL-SELV)
Hold time, select signals
(3)
valid after HSTROBE low 5 ns
17 t
su(HDV-HSTBH)
Setup time, host data valid before HSTROBE high 6 ns
18 t
h(HSTBH-HDV)
Hold time, host data valid after HSTROBE high 0 ns
37 t
su(HCSL-HSTBL)
Setup time, HCS low before HSTROBE low 0 ns
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
38 t
h(HRDYL-HSTBL)
inactivated until HRDY is active (low); otherwise, HPI writes will not 0 ns
complete properly.
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) M = HPI module clock period = 6 * CPU clock period or 12 ns at 500 MHz. (This duration will be much longer when PLL1 is in bypass
mode.)
(3) Select signals (SELV) include: HCNTL[1:0] and HR/W and HHWIL.
184 C64x+ Peripheral Information and Electrical Specifications Copyright © 20092011, Texas Instruments Incorporated
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