Datasheet

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25
23
19
18
22
27
20
21
17
18
28
Stop Start Repeated
Start
Stop
SDA
SCL
16
26 24
TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
Table 7-52. Switching Characteristics Over Recommended Operating Conditions for I2C Output
(see Figure 7-40)
500/625/700
NO. PARAMETER STANDARD MODE FAST MODE UNIT
MIN MAX MIN MAX
16 t
c(SCL)
Cycle time, SCL 10 2.5 μs
Delay time, SCL high to SDA low (for a
17 t
d(SCLH-SDAL)
4.7 0.6 μs
repeated START condition)
Delay time, SDA low to SCL low (for a START
18 t
d(SDAL-SCLL)
4 0.6 μs
and a repeated START condition)
19 t
w(SCLL)
Pulse duration, SCL low 4.7 1.3 μs
20 t
w(SCLH)
Pulse duration, SCL high 4 0.6 μs
21 t
d(SDAV-SDLH)
Delay time, SDA valid to SCL high 250 100 ns
Valid time, SDA valid after SCL low (For I2C
22 t
v(SDLL-SDAV)
0 0 0.9 μs
bus™ devices)
Pulse duration, SDA high between STOP and
23 t
w(SDAH)
4.7 1.3 μs
START conditions
24 t
r(SDA)
Rise time, SDA 1000 20 + 0.1C
b
(1)
300 ns
25 t
r(SCL)
Rise time, SCL 1000 20 + 0.1C
b
(1)
300 ns
26 t
f(SDA)
Fall time, SDA 300 20 + 0.1C
b
(1)
300 ns
27 t
f(SCL)
Fall time, SCL 300 20 + 0.1C
b
(1)
300 ns
Delay time, SCL high to SDA high (for STOP
28 t
d(SCLH-SDAH)
4 0.6 μs
condition)
29 C
b
(1)
Capacitance for each I2C pin 10 10 pF
(1) C
b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Figure 7-40. I2C Output Timing
182 C64x+ Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated
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