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CLKIN2
2
3
4
4
5
1
TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
7.9.4 PLL2 Controller Input Clock Electrical Data/Timing
Table 7-42. Timing Requirements for CLKIN2 Devices
(see Figure 7-33)
500/625/700
PLL MODE
NO. UNIT
x20
MIN MAX
1 t
c(CLKIN2)
Cycle time, CLKIN2 40 40 ns
2 t
w(CLKIN2H)
Pulse duration, CLKIN2 high 0.4 * t
c(CLKIN2)
ns
3 t
w(CLKIN2L)
Pulse duration, CLKIN2 low 0.4 * t
c(CLKIN2)
ns
4 t
t(CLKIN2)
Transition time, CLKIN2 1.2 ns
5 t
J(CLKIN2)
Period jitter (peak-to-peak), CLKIN2 100 ps
Figure 7-33. CLKIN2 Timing
Copyright © 2009–2011, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 171
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