Datasheet

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TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
7.9.3.2 PLL2 PLL Control Register (PLLCTL)
The PLL control register (PLLCTL) is shown in Figure 7-27 and described in Table 7-35.
31 16
Reserved
R-00 0001h
15 8 7 6 5 4 3 2 1 0
PLL
Reserved Rsvd Rsvd Reserved PLLRST Rsvd PLLEN
PWRDN
R-00 0001h R/W-0 R-1 R/W-10 R/W-1 R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-27. PLL Control Register (PLLCTL)
Table 7-35. PLL Control Register (PLLCTL) Field Descriptions
(1)
Bit Field Value Description
31:8 Reserved Reserved. The reserved bit location is always read as 00 0001h. A value written to this field has no
effect.
7 Reserved Reserved. Writes to this register must keep this bit as 0.
6 Reserved Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
5:4 Reserved Reserved. Writes to this register must always program these bits as 00.
3 PLLRST PLL reset bit
0 PLL reset is released
1 PLL reset is asserted
2 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
1 PLLPWRDN PLL power-down mode select bit
0 PLL is operational
1 PLL is placed in power-down state, i.e., all analog circuitry in the PLL is turned-off
0 PLLEN PLL enable bit
0 Bypass mode. PLL is bypassed. All the system clocks (SYSCLKn) are divided down directly from
input reference clock.
1 PLL mode. PLL is not bypassed. PLL output path is enabled. All the system clocks (SYSCLKn) are
divided down from PLL output.
(1) The value of this register is changed by the ROM bootloader.
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