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CLKIN1
2
3
4
4
5
1
SYSCLKOUT
2
3
1
TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
7.8.4 PLL1 Controller Input and Output Clock Electrical Data/Timing
Table 7-29. Timing Requirements for CLKIN1 Devices
(see Figure 7-23)
500/625/700
PLL MODES
NO. UNIT
x10 to x32
MIN MAX
1 t
c(CLKIN1)
Cycle time, CLKIN1 20 80 ns
2 t
w(CLKIN1H)
Pulse duration, CLKIN1 high 0.4 * t
c(CLKIN1)
ns
3 t
w(CLKIN1L)
Pulse duration, CLKIN1 low 0.4 * t
c(CLKIN1)
ns
4 t
t(CLKIN1)
Transition time, CLKIN1 1.2 ns
5 t
J(CLKIN1)
Period jitter (peak-to-peak), CLKIN1 100 ps
Figure 7-23. CLKIN1 Timing
Table 7-30. Switching Characteristics Over Recommended Operating Conditions for
SYSCLKOUT [CPU/6]
(1)(2)
(see Figure 7-24)
500/625/700
NO. PARAMETER UNIT
TYP
1 t
c(CLK)
Cycle time, SYSCLKOUT 6P ns
2 t
w(CLKH)
Pulse duration, SYSCLKOUT high 3P ns
3 t
w(CLKL)
Pulse duration, SYSCLKOUT low 3P ns
(1) The reference points for the rise and fall transitions are measured at 3.3 V V
OL
MAX and V
OH
MIN.
(2) P = 1/CPU clock frequency in nanoseconds (ns).
Figure 7-24. SYSCLKOUT Timing
160 C64x+ Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated
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