Datasheet

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TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
7.8.3.6 PLL1 PLL Controller Command Register (PLLCMD)
The PLL controller command register (PLLCMD) controls the SYSCLK rate change and phase alignment.
The PLLCMD register is shown in Figure 7-19 and described in Table 7-25.
31 16
Reserved
R-0
15 2 1 0
Reserved Rsvd GOSET
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-19. PLL Controller Command Register (PLLCMD)
Table 7-25. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit Field Value Description
31:1 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0 GOSET GO operation command for SYSCLK rate change and phase alignment. Before setting this bit to 1
to initiate a GO operation, check the GOSTAT bit in the PLLSTAT register to ensure all previous
GO operations have completed.
0 No effect. Write of 0 clears bit to 0.
1 Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further
writes of 1 can initiate the GO operation.
156 C64x+ Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated
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