Datasheet

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TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
7.8.3.4 PLL1 PLL Multiply Control Register (PLLM)
The PLL multiplier control register (PLLM) defines the input reference clock frequency multiplier. The
multiplier should be chosen such that the output frequency should not exceed device frequency; i.e., no
more than 700 MHz for the 700-MHz device. The PLLM register is shown in Figure 7-16 and described in
Table 7-23.
31 5 4 0
Reserved PLLM
R-0 R/W-13h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-17. PLL Multiply Control Register (PLLM)
Table 7-23. PLL Multiply Control Register (PLLM) Field Descriptions
Bit Field Value Description
31:5 Reserved Reserved.
4:0 PLLM PLL1 Multiplier Bits
Defines the frequency multiplier of the input reference clock (CLKIN1).
09h - 1Fh x10 - x32 multiplier rate (multiplier is value + 1)
7.8.3.5 PLL1 PLL Controller Divider Register (PLLDIV10)
The (SYSREFCLK) frequency is divided by PLLDIV10 to get SYSCLK10. The PLL controller divider
register (PLLDIV10) is shown in Figure 7-18 and described in Table 7-24.
31 16
Reserved
R-0
15 14 5 4 0
DnEN Reserved RATIO
R/W-1 R-0 R/W-3
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-18. PLL Controller Divider Register (PLLDIV10)
Table 7-24. PLL Controller Divider Register (PLLDIV10) Field Descriptions
Bit Field Value Description
31:16 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
15 DnEN Divider Dn enable bit.
0 Divider n is disabled. No clock output.
1 Divider n is enabled.
14:5 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
4:0 RATIO 0-1Fh Divider ratio bits.
0 Reserved
1h Reserved
2h-1Fh ÷3 to ÷32. Divide frequency by 3 to divide frequency by 32.
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