Datasheet

PRODUCTPREVIEW
TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
7.7.8 Reset Electrical Data/Timing
NOTE
If a configuration pin must be routed out from the device, the internal pullup/pulldown
(IPU/IPD) resistor should not be relied upon; TI recommends the use of an external
pullup/pulldown resistor.
For Figure 7-9, note the following:
• Low group pins consist of all 3.3-V I/O/Z and O/Z pins that have active internal pull-down (IPD)
resistors. These pins become low as soon as the DV
DD33
power supply has reached normal operating
conditions. (These pins are high impedance prior to DV
DD33
reaching a valid level.) These pins remain
low until configured otherwise by their respective peripheral. For a list of pins containing IPD resistors,
see Table 2-5, Terminal Functions.
• High group pins consist of all 3.3-V I/O/Z and O/Z pins that have active internal pull-up (IPU) resistors.
These pins become high as soon as the DV
DD33
power supply has reached normal operating
conditions. (These pins are high impedance prior to DV
DD33
reaching a valid level.) These pins remain
high until configured otherwise by their respective peripheral. For a list of pins containing IPU resistors,
see Table 2-5, Terminal Functions.
• Z group pins consist of all I/O/Z and O/Z pins associated with I2C, RGMII, DDR2 and RapidIO, as well
as 3.3-V pins that have IPU/IPD functionality disabled by one of the six multiplexed GPIO pins. These
pins are high impedance prior to power supply ramp and remain that way when their respective power
supply has reached normal operating conditions. These pins remain in high impedance until configured
otherwise by their respective peripheral.
• Each peripheral must be enabled through software to use it following a Power-on Reset; for more
details, see Section 7.7.1, Power-on Reset, of this document.
• For power-supply sequence requirements, see Section 7.3.1, Power-Supply Sequencing.
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