Datasheet

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TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
7.7 Reset Controller
The reset controller detects the different type of resets supported on the C6472 device and manages the
distribution of those resets throughout the device.
The C6472 device has several types of resets: power-on reset, system reset, warm reset, CPU local reset,
and module reset. Table 7-12 explains further the types of reset, the reset initiator, and the effects of each
reset on the chip. See Section 7.7.8, Reset Electrical Data/Timing, for more information on the effects of
each reset on the PLL controllers and their clocks.
Table 7-12. Reset Types
TYPE INITIATOR EFFECT(s)
POR pin Resets the entire chip including the emulation logic.
Device configuration inputs are latched. Memory contents are not
Power-on Reset
preserved.
Device reset status output (RESETSTAT) pin asserted (low).
Reset on all chip components, except for emulation and PLL3.
Device configuration inputs are latched. Memory contents are not
Warm Reset RESET pin
preserved.
Device reset status output (RESETSTAT) pin asserted (low).
A system reset maintains memory contents and does not reset the
emulation logic.
Emulator The device configuration pins are not re-latched and the state of the
System Reset
Watchdog timer timeout peripherals (enabled/disabled) is not affected.
This is a software-initiated reset that has the effect of a warm reset.
Device reset status output (RESETSTAT) pin asserted (low).
Provides a local reset of the C64x+ megamodule only.
LRESET pin Memory contents are maintained.
C64x+ Megamodule
PSC The device configuration pins are not re-latched.
Local Reset
Watchdog timer timeout C64x+ megamodule slave DMA port remains alive when the C64x+
megamodule is in local reset.
Module Reset Software (PSC MMR bit) Only the module controlled by the LPSC gets reset
7.7.1 Power-on Reset
Power-on Reset is initiated by the POR pin and is used to reset the entire chip, including the emulation
logic. Power-on Reset is also referred to as a cold reset since the device usually goes through a power-up
cycle. During power-up, the POR pin must be asserted (driven low) until the power supplies have reached
their normal operating conditions. Note that a device power-up cycle is not required to initiate a Power-on
Reset.
The following sequence must be followed during a Power-on Reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted
(driven low). While POR is asserted, all output buffers are set to high-impedance and the internal
pull-up and pull-down resistors, on those buffers that have them, are enabled (except for those
disabled by the six multiplexed GPIO pins). All peripherals, except those selected for boot purposes,
are disabled after a power-on reset and must be enabled through the device state control registers; for
more details, see Section 3.3, Peripheral Selection After Device Reset.
2. Once all the power supplies are within valid operating conditions, the POR pin must remain asserted
(low) for a minimum of 256 CLKIN cycles; where CLKIN is the slowest of the active inputs CLKIN1,
CLKIN2, and CLKIN3. The PLL1 controller input clock (CLKIN1), the PLL2 controller input clock
(CLKIN2), and the PLL3 controller input clock (CLKIN3) must be valid during this time, if they are used.
If the DDR2 memory controller is not needed, CLKIN3 can be tied low. Similarly, if the EMAC
peripheral is not needed, CLKIN2 can be tied low. If both CLKIN2 and CLKIN3 are tied low, the POR
pin must remain asserted (low) for a minimum of 256 CLKIN1 cycles after all power supplies have
reached valid operating conditions.
Copyright © 2009–2011, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 141
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