Datasheet

PRODUCTPREVIEW
1
HOUT
(output)
2
TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
7.6.2 NMI Pin-Generated Interrupts
An NMI interrupt may be asserted to individual C64x+ megamodules from the device pins. The NMI
interrupt is initiated by asserting the NMI input (low), selecting the intended C64x+ megamodule(s) with
the CORESEL[2:0] inputs, and then latching it with the rising LRESETNMIEN input. The NMI interrupt
input must be removed (or de-asserted) from the C64x+ megamodule. This is done by the NMI pin being
latched high by the rising LRESETNMIEN input while selecting the intended C64x+ megamodule with the
CORESEL[2:0] inputs. Therefore, to assert and de-assert NMI, two LRESETNMIEN pulses are required
where the first latches NMI low and the second latches NMI high. Timing requirements for NMI can be
found in Table 7-16 and Figure 7-12.
7.6.3 GPIO Pin-Generated Interrupts
The C6472 device has 16 GPIOs. All GPIOs can be configured to generate interrupts. GPIO0-5 provide
interrupts that are assigned one per core. Interrupts from GPIO6-15 are available to all cores. GPIO0-7
are also provided as event inputs to the EDMA. Timing for the GPIO interrupts can be found in
Table 7-152 and Figure 7-65.
7.6.4 Host and Inter-DSP Interrupts
The C64x+ megamodules can assert an event to a host processor using HOUT. Table 7-11 provides the
timing for the HOUT pulses. The external host or any of the six C64x+ megamodules can generate
interrupts to other C64x+ megamodules. For more details, see Section 3.7.
Table 7-11. Switching Characteristics Over Recommended Operating Conditions for HOUT External
Event
(1)
(see Figure 7-7)
500/625/700
NO. UNIT
MIN TYP MAX
1 t
w(HOUTH)
HOUT pulse duration high 24P ns
2 t
w(HOUTL)
HOUT pulse duration low 24P ns
(1) P = 1/CPU clock frequency in nanoseconds (ns).
Figure 7-7. HOUT External Event
140 C64x+ Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated
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