Datasheet

PRODUCTPREVIEW
TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
Table 7-10. C6472 DSP Interrupts (continued)
EVENT NUMBER INTERRUPT EVENT INTERRUPT SOURCE
81 GPINT13 GPIO Interrupt
82 GPINT14 GPIO Interrupt
83 GPINT15 GPIO Interrupt
84 IPC_LOCAL Inter-DSP Interrupt (from IPCGRx register)
85 HPI_INT Host Common Interrupt (from DSPINT bit of the HPIC register)
86 Reserved
87 CPUINT0 Interrupt from CPU0
88 CPUINT1 Interrupt from CPU1
89 CPUINT2 Interrupt from CPU2
90 CPUINT3 Interrupt from CPU3
91 CPUINT4 Interrupt from CPU4
92 CPUINT5 Interrupt from CPU5
93 L2PDWAKE L2 Wake Interrupt
94 - 95 Reserved
96
(5)
INTERR Dropped CPU Interrupt Event
97
(5)
EMC_IDMAERR Invalid IDMA Parameters
98
(5)
PBISTINT PBIST Interrupt
99 - 112 Reserved
113
(5)
PMC_ED Single Bit Error Detected During DMA Read
114 - 115 Reserved
116
(5)
UMC_ED1 Corrected Bit Error Detected
117
(5)
UMC_ED2 Uncorrected Bit Error Detected
118
(5)
PDC_INT Power Down Sleep Interrupt
119 Reserved
120
(5)
PMC_CMPA CPU Memory Protection Fault
121
(5)
PMC_DMPA DMA Memory Protection Fault
122
(5)
DMC_CMPA CPU Memory Protection Fault
123
(5)
DMC_DMPA DMA Memory Protection Fault
124
(5)
UMC_CMPA CPU Memory Protection Fault
125
(5)
UMC_DMPA DMA Memory Protection Fault
126
(5)
EMC_CMPA CPU Memory Protection Fault
127
(5)
EMC_BUSERR Bus Error Interrupt
(5) This system event is generated from within the C64x+ megamodule.
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