Datasheet

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TMS320C6472
www.ti.com SPRS612G–JUNE 2009– REVISED JULY 2011
Table 5-3. Available Memory Page Protection Scheme with Privilege ID (continued)
CORRESPONDING FIELD IN
PRIVID MODULE MEMORY PROTECTION PAGE PRIVILEGE MODE DESCRIPTION
ATTRIBUTE REGISTERS
1 AID1 Inherited from CPU
(1)
C64x+ Megamodule Core 1
2 AID2 Inherited from CPU
(1)
C64x+ Megamodule Core 2
3 AID3 Inherited from CPU
(1)
C64x+ Megamodule Core 3
4 AID4 Inherited from CPU
(1)
C64x+ Megamodule Core 4
5 AID5 Inherited from CPU
(1)
C64x+ Megamodule Core 5
6 (Core 0, AIDX Reserved Reserved
silicon revisions ≤1.2)
6 (Core 0, AIDX Inherited from CPU
(1)
C64x+ Megamodule Core 0
silicon revisions >1.2)
>6 AIDX Reserved Reserved
Table 5-4. Available Memory Page Protection Scheme with AIDx and Local Bits
PRIVID MODULE LOCAL BIT DESCRIPTION
0 0 No access to memory page is permitted.
0 1 Only direct access by CPU is permitted.
1 0 Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA
accesses initiated by the CPU).
1 1 All accesses permitted
Faults are handled by software in an interrupt (or exception, programmable within each C64x+
Megamodule interrupt controller) service routine. A CPU or DMA access to a page without the proper
permissions will:
• Block the access - reads return zero, writes are voided.
• Capture the initiator in a status register - ID, address, and access type are stored.
• Signal event to CPU interrupt controller.
The software is responsible for taking corrective action to respond to the event and resetting the error
status in the memory controller.
For more information on memory protection for L1D, L1P, and L2, see the TMS320C64x+ DSP
Megamodule Reference Guide (literature number SPRU871).
5.3 Bandwidth Management
When multiple requestors contend for a single C64x+ Megamodule resource, the conflict is solved by
granting access to the highest priority requestor. The following four resources are managed by the
Bandwidth Management control hardware:
• Level 1 Program (L1P) SRAM/Cache
• Level 1 Data (L1D) SRAM/Cache
• Level 2 (L2) SRAM/Cache
• Memory-mapped registers configuration bus
The priority level for operations initiated within the C64x+ Megamodule; e.g., CPU-initiated transfers,
user-programmed cache coherency operations, and IDMA-initiated transfers, are declared through
registers in the C64x+ Megamodule. The priority level for operations initiated outside the C64x+
Megamodule by system peripherals is declared through the Priority Allocation Register (PRI_ALLOC), see
Figure 4-2. System peripherals with no fields in PRI_ALLOC have their own registers to program their
priorities.
More information on the bandwidth management features of the C64x+ Megamodule can be found in the
TMS320C64x+ DSP Megamodule Reference Guide (literature number SPRU871).
Copyright © 2009–2011, Texas Instruments Incorporated C64x+ Megamodule 101
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