Datasheet

PRODUCTPREVIEW
TMS320C6472
SPRS612G–JUNE 2009– REVISED JULY 2011 www.ti.com
5.2 Memory Protection Support
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P,
and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16
pages of L1P (2KB each), 16 pages of L1D (2KB each), and up to 64 pages of L2. The L1D, L1P, and L2
memory controllers in the C64x+ Megamodule are equipped with a set of registers that specify the
permissions for each memory page. For L2, the number of protection pages and their sizes depend on the
L2 configuration of the device, as defined in the previous section. The actual sizes are listed in Table 5-2.
Table 5-2 shows the memory addresses used to access the L2 memory.
Table 5-2. L2 Memory Protection Page Sizes
L2
C64x+ C64x+ C64x+ C64x+ C64x+ C64x+
ADDRESS
MEGAMODULE MEGAMODULE MEGAMODULE MEGAMODULE MEGAMODULE MEGAMODULE
CORE 0 CORE 1 CORE 2 CORE 3 CORE 4 CORE 5
Shared L2
0020 0000h - 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB
002B FFFFh
002C 0000h - N/A N/A N/A N/A N/A N/A
002F FFFFh
Local L2
0080 0000h - 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB
0089 7FFFh
0089 8000h - N/A N/A N/A N/A N/A N/A
008F FFFFh
Each page may be assigned with fully orthogonal user and supervisor read, write, and execute
permissions. Additionally, a page may be marked as either (or both) locally or globally accessible. A local
access is a direct CPU access to L1D, L1P, and L2, while a global access is initiated by a DMA (either
IDMA or the EDMA3) or by other system masters.
The assignment of privilege IDs for CPU 0 and all non-EDMA system masters is based on silicon revision.
For silicon revisions ≤1.2, CPU 0 and all non-EDMA system masters on the device are assigned the same
privilege ID of 0. For silicon revsions >1.2, CPU 0 is assigned the privilege ID of 6 and all non-EDMA
system masters are assigned the same privilege ID of 0. CPUs 1-5 are each assigned a unique privilege
ID (see Table 5-3). It is only possible to specify whether the memory pages are locally or globally
accessible. The AIDx (x=0,1,2,3,4,5, or X) and LOCAL bits of the memory protection page attribute
registers specify the memory page protection scheme as listed in Table 5-4.
Whenever the CPU is the initiator of a memory transaction, the privilege mode (user or supervisor) in
which the CPU is running at that time is carried with those transactions. This includes EDMA3 transfers
that are programmed by the CPU. For most peripheral masters (EMAC0, EMAC1, UTOPIA, TSIP0, TSIP1,
and TSIP2), the privilege mode is always user mode. Two peripherals (HPI and SRIO) have
programmable privilege modes through a chip-level register, HOSTPRIV, and can be either user or
supervisor.
Table 5-3. Available Memory Page Protection Scheme with Privilege ID
CORRESPONDING FIELD IN
PRIVID MODULE MEMORY PROTECTION PAGE PRIVILEGE MODE DESCRIPTION
ATTRIBUTE REGISTERS
0 (Core 0, AID0 Inherited from CPU
(1)
C64x+ Megamodule Core 0
silicon revisions ≤1.2)
0 (not SRIO or HPI or Core 0) AID0 User All peripheral masters except
SRIO and HPI
0 (SRIO or HPI) AID0 User/Supervisor (configured in SRIO and HPI
HOSTPRIV)
(1) Also applies to EDMA transfers that are programmed by the CPU.
100 C64x+ Megamodule Copyright © 2009–2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s) :TMS320C6472