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PRODUCTPREVIEW

TMS320C6472

www.ti.com

SPRS612G–JUNE 2009– REVISED JULY 2011

TMS320C6472 Fixed-Point Digital Signal Processor

1 Features

Congestion Control

• Six On-Chip TMS320C64x+ Megamodules

• IEEE 1149.6 Compliant I/Os

• Endianess: Little Endian, Big Endian

– UTOPIA

• C64x+ Megamodule Main Features:

• UTOPIA Level 2 Slave ATM Controller

– High-Performance, Fixed-Point

TMS320C64x+ DSP • 8/16-Bit Transmit and Receive

Operations up to 50 MHz per Direction

– 500/625/700 MHz

• User-Defined Cell Format up to 64 Bytes

– Eight 32-Bit Instructions/Cycle

– Two 10/100/1000 Mb/s Ethernet MACs

– 4000 MIPS/MMACS (16-Bits) at 500 MHz

(EMACs)

– Dedicated SPLOOP Instruction

• Both EMACs are IEEE 802.3 Compliant

– Compact Instructions (16-Bit)

• EMAC0 Supports:

– Instruction Set Enhancements

– MII, RMII, SS-SMII, GMII, and RGMII

– Exception Handling

– 8 Independent Transmit (TX)

– L1/L2 Memory Architecture:

Channels

• 256K-Bit (32K-Byte) L1P Program

– 8 Independent Receive (RX)

RAM/Cache [Direct Mapped, Flexible

Channels

Allocation]

• EMAC1 Supports:

• 256K-Bit (32K-Byte) L1D RAM/Cache

– RMII, SS-SMII and RGMII

[2-Way Set-Associative, Flexible

Allocation] – 8 Independent Transmit (TX)

Channels

• 4.75M-Bit (608K-Byte) L2 Unified Mapped

RAM/Cache [4-Way Set-Associative, – 8 Independent Receive (RX)

Flexible Allocation] Channels

• L1P Memory Controller • Both EMACs (EMAC0 and EMAC1) Share

MDIO Interface

• L1D Memory Controller

– 16-Bit Host-Port Interface (HPI)

• L2 Memory Controller

– One Inter-Integrated Circuit (I

C) Bus

– Time Stamp Counter

– Six Shared 64-Bit General-Purpose Timers

– One 64-Bit General-Purpose/Watchdog Timer

• System PLL and PLL Controller

• Shared Peripherals and Interfaces

• Secondary PLL and PLL Controller, Dedicated

– EDMA Controller

to EMAC

(64 Independent Channels)

• Third PLL and PLL Controller Dedicated to

– Shared Memory Architecture

DDR2 Memory Controller

• Shared L2 Memory Controller

• 16 General-Purpose I/O (GPIO) Pins

• 768K-Byte of RAM

• IEEE-1149.1 (JTAG™)

• Boot ROM

Boundary-Scan-Compatible

– Three Telecom Serial Interface Ports (TSIPs)

• 737-Pin Ball Grid Array (BGA) Package

• Each TSIP is 8 Links of 8 Mbps per

(CTZ or ZTZ Suffix), 0.8-mm Ball Pitch

Direction

• 0.09-μm/7-Level Cu Metal Process (CMOS)

– 32-Bit DDR2 Memory Controller (DDR2-533

• 3.3-, 1.8-, 1.5-, 1.2-V I/O Supplies

SDRAM)

• 1.0-/1.1-, 1.2-V Core Supplies

• 256 M-Byte x 2 Addressable Memory

• Commercial Temperature [0°C to 85°C]

Space

• Extended Temperature [-40°C to 100°C]

– Two 1x Serial RapidIO

Links,

v1.2 Compliant

• 1.25-, 2.5-, 3.125-Gbps Link Rates

• Message Passing, DirectIO Support,

Error Management Extensions, and

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW information concerns products in the formative

or design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right

to change or discontinue these products without notice.

Summary of content (269 pages)

PAGE 1
TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com TMS320C6472 Fixed-Point Digital Signal Processor 1 Features • • • • • • • • • • • Congestion Control • IEEE 1149.6 Compliant I/Os – UTOPIA • UTOPIA Level 2 Slave ATM Controller • 8/16-Bit Transmit and Receive Operations up to 50 MHz per Direction • User-Defined Cell Format up to 64 Bytes – Two 10/100/1000 Mb/s Ethernet MACs (EMACs) • Both EMACs are IEEE 802.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 1.1 www.ti.com CTZ/ZTZ BGA Package (Bottom View) The TMS320C6472 devices are designed for a package temperature range of 0°C to 85°C (commercial temperature range) or -40°C to 100°C (extended temperature range). NOTE Extended temperature (A) range is available only on 500-MHz and 625-MHz devices.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 1.2 Description The TMS320C6472 device is a Texas Instruments next-generation fixed-point digital signal processor (DSP) targeting high-performance computing applications, including high-end industrial, mission-critical, high-end image and video, communication, media gateways, and remote access servers. This device was designed with these applications in mind.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 1.3 www.ti.com Functional Block Diagram Figure 1-2 shows the functional block diagram of the C6472 device. DDR2 SDRAM 32 DDR2 Memory Controller DSP Subsystem 5 DSP Subsystem 4 DSP Subsystem 3 PLL3 and PLL3 Controller DSP Subsystem 2 DSP Subsystem 1 Serial RapidIO DSP Subsystem 0 Boot ROM L2 SRAM/Cache 608K Bytes 4-Way Set Assoc.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Features 3.5 4 5 Power-Down Control 102 5.5 Megamodule Resets 102 6.1 6.2 6.3 7 RMIIn Reset Registers (RMIIRESET0 and RMIIRESET1) ...................................... 74 ........................ 75 3.7 Host and Inter-DSP Interrupt Registers ............ 78 3.8 Timer Event Manager Registers .................... 83 3.9 Reset and Boot Registers .......................... 85 3.10 JTAG ID Register Description ......................
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This revision history highlights the technical changes made to the document in this revision. C6472 Revisions SEE Section 1 ADDITIONS/MODIFICATIONS/DELETIONS Features: Added CTZ package to Features list item Section 1.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 2 Device Overview NOTE Unless otherwise noted, all address locations in this document are stated in hexidecimal numbers. 2.1 Device Characteristics Table 2-1, provides an overview of the C6472 DSP. The table shows significant features of the C6472 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 2-1.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-1. Characteristics of the C6472 Processor (continued) HARDWARE FEATURES Product Status (1) Product Preview (PP), Advance Information (AI), or Production Data (PD) Device Part Numbers (For more details on the C64x+™ DSP part numbering, see Figure 2-13) (1) 2.2 C6472 PP TMX320C6472 PRODUCT PREVIEW information concerns products in the formative or design phase of development.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com • • • Instruction Set Enhancements - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication. Exception Handling - Intended to aid the programmer in isolating bugs.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com src1 Odd register file A (A1, A3, A5...A31) src2 .L1 odd dst Even register file A (A0, A2, A4...A30) (D) even dst long src ST1b ST1a 8 32 MSB 32 LSB long src 8 even dst odd dst .S1 src1 Data path A (D) src2 .M1 dst2 dst1 src1 32 32 src2 LD1b LD1a (A) (B) (C) 32 MSB 32 LSB dst DA1 .D1 src1 PRODUCT PREVIEW src2 2x 1x .D2 LD2a LD2b Odd register file B (B1, B3, B5...B31) src2 DA2 src1 dst 32 LSB 32 MSB src2 .
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 2.3 Memory Map Summary Table 2-2 shows the memory map address ranges of the C6472 device. This table provides a combined view of both local and global addresses. The C64x+ megamodule local memories have both local and global addresses. The megamodule registers only have local addresses. Local addresses can only be resolved within the megamodule. They cannot be accessed from outside the megamodule.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-2.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-2. C6472 Memory Map Summary (continued) MEMORY BLOCK DESCRIPTION Reserved RapidIO Descriptor Memory Reserved BLOCK SIZE (BYTES) HEX ADDRESS RANGE 768K 02D40000 - 02DFFFFF 16K 02E00000 - 02E03FFF 209M + 1008K 02E04000 - 0FFFFFFF Reserved 2M 10000000 - 101FFFFF SL2 RAM (through DSP0) 768K 10200000 - 102BFFFF Reserved 5.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-2.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-3.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-3.
PAGE 17
TMS320C6472 • • • • • corresponding C64x+ megamodule. This transition causes the Boot Controller to bring the C64x+ megamodule core out of the "held-in-reset" state. The CPU then begins execution from the internal L2 SRAM address programmed in the DSP_BOOT_ADDRx register. All memory may be written to and read by the host. This allows for the host to verify what it sends to the DSP, if required. For the C6472 device, only the Host Port Interface (HPI) peripheral can be used for host boot.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com After reset, the C64x+ megamodule core 0 comes out of RESET and starts executing the shared ROM code from the address provided by the Boot Controller based on the UTOPIA boot mode selection (0101b, 0110b, 0111b, 1000b). The C64x+ megamodule core 0 configures the UTOPIA and brings the code image into the on-chip memory via the protocol defined.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 2.5 Pin Assignments 2.5.1 Pin Map Figure 2-2 through Figure 2-5 show the C6472 pin assigments in four quadrants (A, B, C, and D).
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 16 17 18 19 www.ti.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 16 17 18 19 20 21 22 23 24 25 26 27 28 29 P VSS CVDD VSS CVDD2 VSS VSS VSS VSS VSS RIORXP0 VSS RIOTXN0 P N CVDD VSS CVDD VSS CVDD2 VSS VSS AVDDT VSS RIORXN0 VSS RIOTXP0 N M VSS CVDD VSS CVDD VSS DVDD33 VSS VSS VSS VSS RSV13 AVDDA1 M L CVDD VSS CVDD VSS CVDD VSS DVDD33 SCL VSS VSS RSV17 RSV16 L K VSS CVDD VSS CVDD VSS DVDD33 VSS DVDD33 SDA SYSCLKOUT CLKIN1 VSS K J VSS DV
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 1 2 3 4 P TX07 TX04 TX06 N VSS DVDD33 GP11/ CFGGP1 M GP00/ HPI_EN GP10/ CFGGP0 GP02/ TSIP0_EN GP12/ CFGGP2 L GP13/ CFGGP3 GP14/ CFGGP4 GP15/ GP07/ K BOOTACTIVE NMI TX03 www.ti.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 2.6 Signal Groups Description LRESETNMIEN CLKIN1 SYSCLKOUT NMI Clock/PLL1 and PLL Controller LRESET CORSEL[2:0] Reset and Interrupts RESETSTAT RESET POR Clock/PLL2 (EMAC) TMS TDO TDI TCLK TRST EMU0 EMU1 · · · EMU14 EMU15 EMU16 EMU17 EMU18 HOUT BOOTACTIVE Clock/PLL3 (DDR2) IEEE Standard 1149.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 32 Data BED[31:0] BECLKOUTP BECLKOUTN BCS0 BCS1 BEA[13:0] BSDCKE Memory Map Space Select 14 Address External Memory I/F Control BSDCAS BSDRAS BSDWE BSDDQSP[3:0] BSDDQM3 BSDDQM2 BSDDQSN[3:0] BSDDQGATE[3:0] Byte Enables BSDDQM1 BSDDQM0 BBA[2:0] PRODUCT PREVIEW Bank Address DDR2 Memory Controller (32-bit Data Bus) Figure 2-8.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com HPI 16 HCNTL0 HCNTL1 Data HAS HR/W HCS HDS1 HDS2 HRDY HINT Register Select Control Half-Word Select HHWIL (HPI16) SCL I2C SDA PRODUCT PREVIEW HD[15:0] Figure 2-10.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Telecom Serial Interface Port TSIP0 TX0[7:0] TR0[7:0] 8 8 Transmit Receive TSIP2 FSA0 Control FSB0 Transmit PRODUCT PREVIEW CLKA0 Clock CLKB0 Receive TSIP1 TX1[7:0] 8 FSA1 FSB1 CLKA1 CLKB1 8 8 TX2[7:0] TR2[7:0] FSA2 Control FSB2 Transmit CLKA2 Clock TR1[7:0] 8 CLKB2 Receive Control Clock Figure 2-12.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 2.7 Terminal Functions The terminal functions table (Table 2-5) identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors and a functional pin description.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) BSDDQGATE3 E14 I/O/Z BSDDQGATE2 B16 I/O/Z BSDDQGATE1 D2 I/O/Z BSDDQGATE0 C2 I/O/Z IPD/IPU (2) (3) DESCRIPTION DDR2 Memory Controller data strobe gate [3:0] RESETS PRODUCT PREVIEW LRESET J4 I IPU External LRESET input pin to assert/de-assert LRESET to the core specified by CORESEL[2:0] is latched when LRESETNMIEN is rising.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) TYPE (1) IPD/IPU (2) (3) DESCRIPTION NO. MRXD06/RMRXER1 AJ13 I IPU EMAC Receive Data 6 (MRXD6) for GMII0 or Receive Error (RXER) for RMII1. Pin function defined by MACSEL0[2:0] and MACSEL1[1:0] (see Table 3-1). MRXD07 AJ6 I IPU EMAC Receive Data 7 (MRXD7) for GMII0. Pin function defined by MACSEL0[2:0] (see Table 3-1).
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) IPD/IPU (2) (3) DESCRIPTION ETHERNET MAC (EMAC) (RGMII[1:0]) RGTXC0 AH19 O EMAC Transmit Clock (TXC) for RGMII0 if enabled by MACSEL0[2:0] (see Table 3-1). O EMAC Transmit Data bus (TD[3:0]) for RGMII0 if enabled by MACSEL0[2:0] (see Table 3-1).
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) IPD/IPU (2) (3) DESCRIPTION JTAG EMULATION/TEST C27 I IPU JTAG test-port clock TDI D27 I IPU JTAG test-port data in TDO C29 O/Z IPU JTAG test-port data out TMS B28 I IPU JTAG test-port mode select TRST C28 I IPD JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG compatibility statement portion of this data sheet.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) RSV15 A20 NC RSV16 L29 NC RSV17 L28 NC RSV18 E19 NC RSV19 E18 NC RSV20 R26 NC RSV21 E26 NC RSV22 B24 NC RSV23 B23 NC RSV24 B9 NC RSV25 A8 NC IPD/IPU (2) (3) DESCRIPTION SUPPLY VOLTAGE MONITOR PINS PRODUCT PREVIEW CVDDMON DVDD15MON DVDD18MON DVDD33MON 40 AE9 Die-side core supply (CVDD) voltage monitor pin.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) IPD/IPU (2) (3) DESCRIPTION SUPPLY VOLTAGE PINS HHV15EN HHV18EN AF13 D20 I When RGMII is used, connect to DVDD15 (1.5V/1.8V) Connected to VSS, if RGMII is not used NOTE: If the RGMII mode of the EMAC is not used, the DVDD15, DVDD15MON, VREFHSTL, PTV15P, PTV15N, and HHV15EN pins can be NC or connected directly to VSS (GND) to save power.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) IPD/IPU (2) (3) DESCRIPTION R12 R14 R16 R18 T11 T13 T15 T17 U10 U12 U14 U16 U18 CVDD V13 V15 V17 I 1-V (500-MHz device), 1.1-V (625-MHz device), 1.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) IPD/IPU (2) (3) DESCRIPTION A25 A28 AA24 AA6 AB2 AB7 AB23 AB28 AC6 AC8 AC10 AC12 AC22 AC24 AD11 PRODUCT PREVIEW AD13 AD23 AD7 DVDD33 AD9 I 3.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) IPD/IPU (2) (3) DESCRIPTION G24 H23 J2 J24 K23 K25 K7 L24 L6 M23 M7 DVDD33 N2 N6 I 3.3-V I/O supply voltage I 1.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME AVDDA3 NO. B21 TYPE (1) A21 PRODUCT PREVIEW V23 DVDDR R28 DESCRIPTION I I 1.8-V DDR analog supply voltage NC or connected to VSS, if DDR is not used NOTE: If the DDR2 Memory Controller is not used, the DVDD18, DVDD18MON, VREFSSTL, AVDDA3, AVDDA4, CVDD1, PTV18P, and PTV18N pins can be NC or connected directly to VSS (GND) to save power.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) N25 AVDDT R25 IPD/IPU (2) (3) DESCRIPTION I 1.2-V RapidIO termination supply voltage NC or connected to VSS, if RapidIO is not used Do not connect this SERDES supply to CVDD1 NOTE: If the RapidIO interface is not used, the CVDD2, AVDDA, DVDDD, DVDDR, and AVDDT pins can be NC or connected directly to VSS (GND) to reduce power use.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 2-5. Terminal Functions (continued) SIGNAL NAME NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 2.8 Development 2.8.1 Development Support For customers that will develop their own features and software on the C6472 device, TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, CTZ), the temperature range (for example, blank is the default commercial temperature range), and the device speed range, in megahertz (for example, blank is 500 MHz). Figure 2-13 provides a legend for reading the complete device name for any TMS320C64x+™ DSP generation member.
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TMS320C6472 SPRU862 TMS320C64x+ DSP Cache User's Guide. Explains the fundamentals of memory caches and describes how the two-level cache-based internal memory architecture in the TMS320C64x+ digital signal processor (DSP) of the TMS320C6000 DSP family can be efficiently used in DSP applications. Shows how to maintain coherence with external memory, how to use DMA to reduce memory latencies, and how to optimize your code to improve cache efficiency.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 PRODUCT PREVIEW 56 www.ti.com SPRUE11 TMS320C6472/TMS320TCI648x DSP Inter-Integrated Circuit (I2C) Module User's Guide. This document describes the inter-integrated circuit (I2C) module in the TMS320C6472/TMS320TCI648x Digital Signal Processor (DSP). The I2C provides an interface between the C6472/TCI648x device and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com SPRAA84 TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included. SPRAAQ4 TMS320C6472/TMS320TCI6486 Hardware Design Guide.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 2.9 www.ti.com Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 3 Device Configuration On the C6472 device, boot mode and certain device configurations/peripheral selections are determined at device reset. Following device reset, the software needs to enable and configure the desired peripheral modules. 3.1 Device Configuration at Device Reset Table 3-1 describes the C6472 device configuration pins. The logic level of these pins is latched at reset to determine the device configuration.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 3.1.1 www.ti.com Debugging Considerations It is recommended that external connections be provided to device configuration pins, including all GPIO, MACSEL, DDREN, and RIOEN pins. Although internal pullup/pulldown resistors exist on these pins, providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. It also improves noise immunity for critical mode control inputs.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 3-2.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 3-2. Device Configuration Registers (Chip-Level Registers) (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS BOOT CONTROLLER REGISTERS 02AB 0000 02AB 0004 02AB 0008 PRODUCT PREVIEW 62 RESET_STAT Reset Status This register tells the status of the local reset for all 6 C64x+ megamodules.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 3.3 Peripheral Selection After Device Reset 3.3.1 Controlling Internal Pulls on the Peripherals 3.3.1.1 Device Control Register (DEVCTL) The device control register (DEVCTL) controls the internal pulls on the I/O interfaces. The bits are initialized on the rising edge of the Power-On Reset from the GPIO pins [5:0], then software can override these latched values.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 3-3. Device Control Register (DEVCTL) Field Descriptions (continued) Bit 9 8 7 6 PRODUCT PREVIEW 5 4 3 2 1 0 64 Field Value TSIP2_EN[0] Description TSIP2 Internal Pulls Enable[0]. Initialized at reset from GP04/TSIP2_EN pin. 0 Enable the pulls on all TSIP2 I/O pins and power down the I/O buffers. When this bit is low, the values of TSIP2_EN[2:1] = don't care.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 3.3.1.2 Device Control Key Register (DEVCTL_KEY) The device control key register (DEVCTL_KEY) protects against inadvertently updating the DEVCTL register with errant software. The DEVCTL_KEY register is shown in Figure 3-2. 31 0 KEY R/W-0000 0000 0000 0000 LEGEND: R/W = Read/Write; -n = value after reset Figure 3-2. Device Control Key Register (DEVCTL_KEY) To update/write the DEVCTL register: 1.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 3.3.1.3 www.ti.com IPU/IPD Control This section augments Table 3-3 in Section 3.3.1.1. It contains more detail about the operation of the internal resistor pulls and the output buffer operation. It explicitly lists the relevant pins individually under all possible configurations and states whether internal pull resistors are enabled or disabled. The 3.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 3-5.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 3-6.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 3-7.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 3-8.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 3-9.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 3-9.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 3.4 Device Status Register (DEVSTAT) The device status register (DEVSTAT) depicts the status of the device configuration inputs that were captured at device reset. The DEVSTAT register is shown in Figure 3-3.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 3.5 www.ti.com RMIIn Reset Registers (RMIIRESET0 and RMIIRESET1) RMII supports switching of 10/100 Mbps modes and switching between half and full-duplex. The RMIIRESET0 and RMIIRESET1 registers are used to reset the RMII interface to switch the speed and duplex settings. The selection of 10/100 Mbps and half- and full-duplex modes is determined by registers in the EMAC modules.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 3.6 3.6.1 Memory Privilege Registers Host Memory Privilege Permission Register (HOSTPRIV) Memory privilege is an extension of the memory protection defined in the C64x+ megamodule. It defines the supervisor user mode privilege required to access peripherals that do not inherently have the protection built in. For more information, see the TMS320C64x+ DSP Megamodule Reference Guide (literature number SPRU871).
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 3.6.2 www.ti.com Memory Privilege Permission Register (PRIVPERM) The memory privilege permission register (PRIVPERM) defines the permission level necessary to access peripheral registers on the CFG SCR. The defaults allow both user- and supervisor-level accesses to these peripheral groups. If desired, the software can override accesses to these peripheral groups by writing the values shown in Table 3-11 to the register bits.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 3.6.3 Key-Based Protection for HOSTPRIV and PRIVPERM Registers (PRIVKEY) Key-based protection of HOSTPRIV and PRIVPERM is provided for a higher level of protection or control over changing the permission levels. The PRIVKEY register, shown in Figure 3-7 and described in Table 3-13, is needed to service the key requirement.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 3.7 3.7.1 www.ti.com Host and Inter-DSP Interrupt Registers NMI Generator Registers (NMIGR0-NMIGR5) The NMI generator registers (NMIGR0-NMIGR5) create an NMI event to each C64x+ megamodule. The NMIGR0 register generates an NMI event to C64x+ Megamodule0, the NMIGR1 register generates an NMI event to C64x+ Megamodule1, etc. Writing a 1 to the NMIG field generates an NMI pulse. Writing a 0 has no effect; reads return 0 and have no other effect.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 3.7.2 Inter-DSP Interrupt Registers (IPCGR0-IPCGR5 and IPCAR0-IPCAR5) The IPCGRn (IPCGR0 thru IPCGR5) and IPCARn (IPCAR0 thru IPCAR5) registers facilitate inter-DSP interrupts. This can be utilized by external hosts or C64x+ megamodules to generate interrupts to other DSPs. A write of 1 to the IPCG field of IPCGRn register generates an interrupt pulse to C64x+ Megamodulen (n = 0-5).
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 3.7.3 Host Interrupt and Event Pulse Generation Registers (IPCGR15 and IPCAR15) The host interrupt and event pulse generation registers (IPCGR15 (or IPCGRH) and IPCAR15 (or IPCARH)) facilitate host CPU interrupt. Operation and use of the IPCGR15 register is the same as registers IPCGR0-5 and the IPCAR15 register is the same as registers IPCAR0-5.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 3.8 3.8.1 Timer Event Manager Registers Timer Pin Manager Register (TPMGR) The timer pin manager register (TPMGR) configures the timer output pin. The TPMGR register details are shown in Figure 3-13 and described in Table 3-18. 31 4 3 0 Reserved TOUTSEL R-0000 0000 0000 0000 0000 0000 0000 R/W-0000 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 3-13. Timer Pin Manager Register (TPMGR) Table 3-18.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 3.8.2 www.ti.com Reset Mux Registers (RSTMUX0-RSTMUX5) The reset controller has inputs for each of the watchdog timer outputs. The reset mux registers determine the method of reset that will be used when a watchdog timeout occurs.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 3.9 Reset and Boot Registers 3.9.1 Reset Status Register (RESET_STAT) The reset status register (RESET_STAT) indicates the status of global (device) reset and of the local reset for all six C64x+ megamodules.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 3.9.2 www.ti.com Boot Complete Status Register (BOOT_COMPLETE_STAT) The boot complete status register (BOOT_COMPLETE_STAT) indicates if the boot process is complete. 31 16 Reserved R-0000 0000 0000 0000 15 5 4 3 2 1 0 Reserved 6 BC5 BC4 BC3 BC2 BC1 BC0 R-00 0000 0000 RS-0 RS-0 RS-0 RS-0 RS-0 RS-0 LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset Figure 3-16.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 3.9.3 Boot Progress Register (BOOTPROGRESS) The boot progress register (BOOTPROGRESS) tracks the progress of the boot sequence. The ROM boot code periodically writes values to this register to indicate progress. This can also be used by other software as a debugging tool. 31 0 BOOTPROGRESS R/W-0000 0000 0000 0000 0000 0000 0000 0000 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 3-17.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 3.9.5 www.ti.com DSP_BOOT_ADDRn Register (DSP_BOOT_ADDR0-DSP_BOOT_ADDR5) Each C64x+ megamodule has its own boot address register (DSP_BOOT_ADDRn) associated with it. The contents of these registers are the 22 MSBs of the initial fetch address of the C64x+ megamodulen from where it starts executing after the boot complete bit is set.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 3.10 JTAG ID Register Description The JTAG ID register is a read-only register that identifies to the customer the JTAG ID (DEVICE_ID). For the C6472 device, the JTAG ID register resides at address location 02A8 0008h. It reads 0009 102Fh. For the actual register bit names and their associated bit field descriptions, see Figure 3-20 and Table 3-24.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 4 System Interconnect On the C6472 device, the C64x+ megamodule, the EDMA3 transfer controllers, and the system peripherals are interconnected through two switch fabrics. The switch fabrics allow for low-latency, concurrent data transfers between peripherals and memories. The switch fabrics also allow for seamless arbitration between the system masters when accessing system slaves. 4.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 4.2 Data Switch Fabric Connections Figure 4-1 shows the connection between slaves and masters through the data switched central resource (SCR). Masters are shown on the right and slaves on the left. The data SCR connects masters to slaves via 128-bit data buses running at frequency equal to the CPU frequency divided by 3. Some peripherals and the C64x+ megamodule have both slave and master ports.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 4-1.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 4.3 www.ti.com Priority Allocation On the C6472 device, DMA data transfers use a priority-based arbitration. The C64x+ megamodule, EDMA, TSIP, and SRIO peripherals define their own priorities. The Ethernet and HPI peripherals do not define their own priorities, while the UTOPIA-PDMA only partially defines its own priority.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 5 C64x+ Megamodule The C64x+ Megamodule consists of several components — the C64x+ CPU, the L1 program and data memory controllers, the L2 memory controller, the internal DMA (IDMA), the interrupt controller, power-down controller, and external memory controller. The C64x+ Megamodule also provides support for memory protection (for L1P, L1D, and L2 memories) and bandwidth management (for resources local to the C64x+ Megamodule).
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com L1D is a two-way set-associative cache while L1P is a direct-mapped cache. The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PCFG) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C64x+ Megamodule. After device reset, L1P and L1D cache are configured as all cache or all SRAM. The on-chip Bootloader changes the reset configuration for L1P and L1D.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com The L2 memory configuration for the C6472 device is as follows: • Port 0 configuration: – Memory size is 608KB – Starting address is 0080 0000h – 2-cycle latency – 4 × 128-bit bank configuration • Port 1 configuration: – Memory size 768K ROM, starting address is 0010 0000h – Memory size is 768KB shared RAM, starting address is 0020 0000h – 1-cycle latency – 4 × 256-bit bank configuration Table 5-1.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com L2 memory can be configured as all SRAM or as part 4-way set-associative cache. The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register (L2CFG) of the C64x+ Megamodule. Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is configured as all SRAM after device reset.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 5.2 www.ti.com Memory Protection Support Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB each), 16 pages of L1D (2KB each), and up to 64 pages of L2.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 5-3.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 5.4 www.ti.com Power-Down Control The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule. The power-down controller (PDC) of the C64x+ Megamodule can be used to power down L1P, the cache control hardware, the CPU, and the entire C64x+ Megamodule. These power-down features can be used to design systems for lower overall system power requirements.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 5.6 Megamodule Revision The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in Figure 5-5 and described in Table 5-6. The C64x+ Megamodule revision is dependant on the silicon revision being used. For more information, see the TMS320C6472 Digital Signal Processor Silicon Errata (literature number SPRZ300).
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 5.7 www.ti.com C64x+ Megamodule Register Descriptions Table 5-7.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 5-7. Megamodule Interrupt Registers (continued) HEX ADDRESS RANGE ACRONYM 0180 0188 INTDMASK 0180 0188 - 0180 01BC - 0180 01C0 EVTASRT 0180 01C4 - 0180 FFFC - REGISTER NAME Dropped Interrupt Mask Register Reserved Event Asserting Register Reserved Table 5-8.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 5-11.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 5-11.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 5-13.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 5-13.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 5-13.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 5-13.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 6 Device Operating Conditions Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) (1) (2) (3) Supply voltage range: CVDD -0.5 V to 1.5 V CVDD2 -0.5 V to 1.5 V DVDD33 -0.5 V to 4.2 V DVDD18, AVDDA3, AVDDA4 -0.5 V to 2.5 V AVDDA1, AVDDA2 -0.5 V to 2.5 V DVDD15 -0.5 V to 2.5 V DVDDR -0.5 V to 2.5 V CVDD1 -0.5 V to 1.5 V AVDDA, DVDDD, AVDDT Input voltage (VI) range: -0.5 V to DVDD33 + 0.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Recommended Operating Conditions (1) 6.2 PARAMETER CVDD Supply voltage, Core CVDD2 Supply voltage, SRIO Core MIN NOM 500 MHz 0.95 1.0 MAX UNIT 1.05 625 MHz 1.05 1.1 1.16 700 MHz 1.14 1.2 1.26 500 MHz 0.95 1.0 1.05 625 MHz 1.05 1.1 1.16 700 MHz 1.14 1.2 1.26 1.14 1.2 1.26 V 3.135 3.3 3.465 V 1.71 1.8 1.89 V V V PRODUCT PREVIEW CVDD1 Supply volttage, 1.2-V DDR Core DVDD33 Supply voltage, 3.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Recommended Operating Conditions(1) (continued) PARAMETER MIN 3.3-V Supply (DVDD33) I/O supply power (2) MAX UNIT 0.2 1.8-V Supplies, including PLLs (DVDD18, AVDDA1, AVDDA2, AVDDA3, AVDDA4 0.26 1.5-V Supplies (DVDD15, DVDDR) 0.05 1.2-V Supplies (CVDD1, AVDDA, DVDDD, AVDDT) 0.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 6.3 www.ti.com Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) TEST CONDITIONS (1) PARAMETER VOH VOL V I2C pins DVDD33 = MIN, IOH = MAX 0.8 * DVDD33 V RGMII pins DVDD15 - 0.4 V DDR2 memory controller pins DVDD18 - 0.4 V 3.3-V pins (except I2C pins) DVDD33 = MIN, IOL = MAX 0.4 V I2C pins Pulled up to 3.3 V, 3 mA sink current 0.4 V RGMII pins 0.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7 C64x+ Peripheral Information and Electrical Specifications 7.1 Parameter Information Tester Pin Electronics 42 W 3.5 nH Transmission Line (A) Z0 = 50 W Data Sheet Timing Reference Point Output Under Test Device Pin 4.0 pF A. (A) 1.85 pF The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839).
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-1. Timing Requirements for Power-Supply Sequence (Option 1) (1) 500/625/700 NO. 1 (1) MIN MAX UNIT tsu(DVDD33-CVDD) Setup time, DVDD33 supply stable before CVDD supply stable 0.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com • PTV15N - connect this pin to the 1.8-V supply via a 200-Ω resistor. When the RapidIO interface is not used, the CVDD2, AVDDA, DVDDD, DVDDR, and AVDDT pins can be NC or connected directly to ground (VSS) to reduce power use. However, this prevents boundary-scan from functioning on the RapidIO pins.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.4.1 PSC Peripheral Register Descriptions Table 7-3.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 7.5 www.ti.com Enhanced Direct Memory Access (EDMA3) Controller The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between external memory and internal memory), performs sorting or subframe extraction of various data structures and offloads data transfers from the device CPU.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-4.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-4.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-5.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-5.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-5.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-5.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-5.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-5. EDMA3 Registers (continued) HEX ADDRESS RANGE ACRONYM ... REGISTER NAME ... 02A0 5FC0 - 02A0 5FDC - Parameter Set 254 02A0 5FE0 - 02A0 5FFC - Parameter Set 255 Table 7-6.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-6.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-7.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-8.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-9.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.6 Interrupts 7.6.1 Interrupt Sources and Interrupt Controller The CPU interrupts on the C6472 device are configured through the C64x+ megamodule interrupt controller. The interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs, the CPU exception input, or the advanced emulation logic. Table 8-4 shows the mapping of system events to the interrupt controller inputs.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-10.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-10.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 7.6.2 www.ti.com NMI Pin-Generated Interrupts An NMI interrupt may be asserted to individual C64x+ megamodules from the device pins. The NMI interrupt is initiated by asserting the NMI input (low), selecting the intended C64x+ megamodule(s) with the CORESEL[2:0] inputs, and then latching it with the rising LRESETNMIEN input. The NMI interrupt input must be removed (or de-asserted) from the C64x+ megamodule.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.7 Reset Controller The reset controller detects the different type of resets supported on the C6472 device and manages the distribution of those resets throughout the device. The C6472 device has several types of resets: power-on reset, system reset, warm reset, CPU local reset, and module reset. Table 7-12 explains further the types of reset, the reset initiator, and the effects of each reset on the chip. See Section 7.7.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com PRODUCT PREVIEW Within the low period of the POR pin, the following happens: – The reset signals flow to the entire chip (including the emulation logic), resetting modules that use reset asynchronously. – The PLL1 controller clocks are started at the frequency of the system reference clock. The clocks are propagated throughout the chip to reset modules that use reset synchronously. By default, PLL1 is in reset and unlocked.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com – The RESETSTAT pin becomes active (low), indicating the device is in reset. 2. The RESET pin may now be released (driven inactive high). When the RESET pin is released, the configuration pin values are latched and the PLL controllers immediately change their system clocks to their default divide-down values. Other device initialization is also started. 3. After device initialization is complete, the RESETSTAT pin goes inactive (high). 4.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 7.7.5 www.ti.com Module Reset Module reset is initiated by LPSC and only resets the module controlled by that LPSC. To prevent stalls, care must be taken when using this reset. 7.7.6 Reset Priority If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priority reset request. The rest request priorities are as follows (high to low): • Power-on Reset • Warm Reset • System Reset • Local Reset 7.7.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.7.8 Reset Electrical Data/Timing NOTE For Figure 7-9, note the following: • Low group pins consist of all 3.3-V I/O/Z and O/Z pins that have active internal pull-down (IPD) resistors. These pins become low as soon as the DVDD33 power supply has reached normal operating conditions. (These pins are high impedance prior to DVDD33 reaching a valid level.) These pins remain low until configured otherwise by their respective peripheral.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Power Supplies Ramping Power Supplies Stable CLKIN1 1 POR RESET 5 RESETSTAT SYSREFCLK (PLL1C) SYSCLK7 SYSCLK8 SYSCLK9 SYSCLK10 PRODUCT PREVIEW 3 Boot and Device Configuration Pins Z Group Undefined Low Group Undefined High-Z 4 Low High High Group Undefined CLKIN2 and CLKIN3 Internal Reset PLL2C Undefined SYSREFCLK (PLL3C) Undefined A. B.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-14. Timing Requirements for Reset (1) (see Figure 7-10 and Figure 7-11) 500/625/700 NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-16. Timing Requirements for Local Reset (1) (see Figure 7-12) 500/625/700 NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.8 PLL1 and PLL1 Controller The C6472 device includes a PLL1 and a software-programmable PLL1 controller. The PLL1 controller is able to generate different clocks for different parts of the system (i.e., megamodule, DSP core, Peripheral Data Bus, and other peripherals). There is no hardware CLKMODE selection on the C6472 device. The PLL multiply factor is set in software after reset.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com PLLV1 PLL1 PLLRST PLLPWRDN PLLM PLLCTL CLKIN1 PLL1 Controller PLLEN 1 Bypass Mode /1 SYSCLK1 /1 SYSCLK2 /1 SYSCLK3 /1 SYSCLK4 /1 SYSCLK5 /1 SYSCLK6 /3 SYSCLK7 /6 SYSCLK8 To SYSCLKOUT /2 SYSCLK9 /3 SYSCLK10 0 PRODUCT PREVIEW (A) DIV10 A. SYSCLK10 is programmable. Figure 7-14.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-18. PLL1 Clock Frequency Ranges REQUIRED FREQUENCY FOR 500-MHz OPERATION REQUIRED FREQUENCY FOR 625-MHz OPERATION REQUIRED FREQUENCY FOR 700-MHz OPERATION UNIT CLKIN1 15.625 - 50.0 19.531 - 50.0 21.875 - 50.0 MHz SYSCLK1 500.0 625.0 700.0 MHz SYSCLK2 500.0 625.0 700.0 MHz SYSCLK3 500.0 625.0 700.0 MHz SYSCLK4 500.0 625.0 700.0 MHz SYSCLK5 500.0 625.0 700.0 MHz SYSCLK6 500.0 625.0 700.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 7.8.2 www.ti.com PLL1 Controller Peripheral Register Descriptions The memory map of the PLL1 controller is shown in Table 7-20. Note that only registers documented here are accessible on the C6472. Other addresses in the PLL1 controller memory map are reserved and should not be modified. Table 7-20.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.8.3 PLL1 Controller Registers This section provides a description of the PLL1 controller registers. For details on the operation of the PLL controller module, see the TMS320C6472/TMS320TCI648x DSP Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature number SPRU806).
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 7.8.3.3 www.ti.com PLL1 PLL Control Register (PLLCTL) The PLL control register (PLLCTL) is shown in Figure 7-16 and described in Table 7-22. 31 16 Reserved R-00 0001h 15 8 7 6 5 4 3 2 1 0 PLLEN R/W-0 Reserved Rsvd Rsvd Reserved PLLRST Rsvd PLL PWRDN R-00 0001h R/W-0 R-1 R/W-10 R/W-1 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-16. PLL Control Register (PLLCTL) Table 7-22.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.8.3.4 PLL1 PLL Multiply Control Register (PLLM) The PLL multiplier control register (PLLM) defines the input reference clock frequency multiplier. The multiplier should be chosen such that the output frequency should not exceed device frequency; i.e., no more than 700 MHz for the 700-MHz device. The PLLM register is shown in Figure 7-16 and described in Table 7-23.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 7.8.3.6 www.ti.com PLL1 PLL Controller Command Register (PLLCMD) The PLL controller command register (PLLCMD) controls the SYSCLK rate change and phase alignment. The PLLCMD register is shown in Figure 7-19 and described in Table 7-25. 31 16 Reserved R-0 15 1 0 Reserved 2 Rsvd GOSET R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-19. PLL Controller Command Register (PLLCMD) Table 7-25.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.8.3.7 PLL1 PLL Controller Status Register (PLLSTAT) The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-20 and described in Table 7-26. 31 16 Reserved R-0000 0000 0000 0000 0000 0000 0000 001 15 1 0 Reserved GOSTAT R-0000 0000 0000 0000 0000 0000 0000 001 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-20.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 7.8.3.8 www.ti.com PLL1 PLLDIV Ratio Change Status Register (DCHANGE) Whenever a different ratio is written to the PLLDIV10 register, the PLLCTRL flags the change in the PLLDIV ratio change status register (DCHANGE). During the GO operation, the PLL controller will only change the divide ratio of the SYSCLK with the bit set in DCHANGE. Note that changed clocks will be automatically aligned to other clocks if the corresponding ALN bit is set.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.8.3.9 PLL1 SYSCLK Status Register (SYSTAT) The SYSCLK status register (SYSTAT) shows the status of the system clocks (SYSCLKn). SYSTAT is shown in Figure 7-22 and described in Table 7-28.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 7.8.4 www.ti.com PLL1 Controller Input and Output Clock Electrical Data/Timing Table 7-29. Timing Requirements for CLKIN1 Devices (see Figure 7-23) 500/625/700 PLL MODES x10 to x32 NO. UNIT MIN MAX 20 80 1 tc(CLKIN1) Cycle time, CLKIN1 2 tw(CLKIN1H) Pulse duration, CLKIN1 high 0.4 * tc(CLKIN1) ns ns 3 tw(CLKIN1L) Pulse duration, CLKIN1 low 0.4 * tc(CLKIN1) ns 4 tt(CLKIN1) Transition time, CLKIN1 1.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.9 PLL2 and PLL2 Controller The C6472 device includes a PLL2 and a software-programmable PLL2 controller. The PLL2 controller generates different clocks required for Gigabit Ethernet. The PLL multiply factor is set to x20 for PLL2.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com PLLV2 PLL2 PLLRST PLLPWRDN PLL2 Controller PLLEN PLLCTL CLKIN2 1 Bypass Mode PRODUCT PREVIEW /2 SYSCLK13 /10,/4 SYSCLK14 /100 SYSCLK15 /2 SYSCLK16 /10 SYSCLK17 /100 SYSCLK18 0 Figure 7-25. PLL2 and PLL2 Controller Table 7-31. PLL2 Clock Frequency Ranges 7.9.1.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-32. PLL2 Stabilization, Lock, and Reset Times MIN PLL2 stabilization time TYP UNIT μs 2000 * C (1) PLL2 lock time 128 * C (1) PLL2 reset time (1) MAX 500 ns ns C = CLKIN2 cycle time in ns. For example, when CLKIN2 frequency is 25 MHz, use C = 40 ns. 7.9.2 PLL2 Controller Peripheral Register Descriptions The memory map of the PLL2 controller is shown in Table 7-33.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 7.9.3 www.ti.com PLL2 Controller Registers This section provides a description of the PLL2 controller registers. For details on the operation of the PLL controller module, see the TMS320C6472/TMS320TCI648x DSP Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature number SPRU806).
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.9.3.2 PLL2 PLL Control Register (PLLCTL) The PLL control register (PLLCTL) is shown in Figure 7-27 and described in Table 7-35. 31 16 Reserved R-00 0001h 15 8 7 6 5 4 3 2 1 0 PLLEN R/W-0 Reserved Rsvd Rsvd Reserved PLLRST Rsvd PLL PWRDN R-00 0001h R/W-0 R-1 R/W-10 R/W-1 R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-27. PLL Control Register (PLLCTL) Table 7-35.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 7.9.3.3 www.ti.com PLL2 PLL Controller Dividern Register (PLLDIVn) The PLL controller divider registers 1 through 6 decide the frequency ratio for SYSCLK13 through SYSCLK18. The PLLDIVn register is shown in Figure 7-28 and described in Table 7-36. 31 16 Reserved R-0 15 14 7 6 0 DnEN Reserved RATIO R/W-1 R-0 R/W-x LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-28.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.9.3.4 PLL2 PLL Controller Command Register (PLLCMD) The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 7-29 and described in Table 7-38. 31 16 Reserved R-0 15 1 0 Reserved 2 Rsvd GOSET R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-29. PLL Controller Command Register (PLLCMD) Table 7-38.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 7.9.3.5 www.ti.com PLL2 PLL Controller Status Register (PLLSTAT) The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-30 and described in Table 7-39. 31 16 Reserved R-0000 0000 0000 0000 0000 0000 0000 001 15 1 0 Reserved GOSTAT R-0000 0000 0000 0000 0000 0000 0000 001 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-30.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.9.3.6 PLL2 PLLDIV Ratio Change Status Register (DCHANGE) Whenever a different ratio is written to the PLLDIVn registers, the PLLCTRL flags the change in the PLLDIV ratio change status registers (DCHANGE). During the GO operation, the PLL controller will only change the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that changed clocks will be automatically aligned to other clocks.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 7.9.3.7 www.ti.com PLL2 SYSCLK Status Register (SYSTAT) The SYSCLK status register (SYSTAT) shows the status of the system clocks (SYSCLKn). SYSTAT is shown in Figure 7-32 and described in Table 7-41. 31 16 Reserved R-0 15 8 Reserved R-0 7 5 4 3 2 1 0 Reserved 6 SYS18ON SYS17ON SYS16ON SYS15ON SYS14ON SYS13ON R-0 R-1 R-1 R-1 R-1 R-1 R-1 LEGEND: R = Read only; -n = value after reset Figure 7-32.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.9.4 PLL2 Controller Input Clock Electrical Data/Timing Table 7-42. Timing Requirements for CLKIN2 Devices (see Figure 7-33) 500/625/700 PLL MODE x20 NO. UNIT MIN MAX 40 40 1 tc(CLKIN2) Cycle time, CLKIN2 ns 2 tw(CLKIN2H) Pulse duration, CLKIN2 high 0.4 * tc(CLKIN2) 3 tw(CLKIN2L) Pulse duration, CLKIN2 low 0.4 * tc(CLKIN2) 4 tt(CLKIN2) Transition time, CLKIN2 1.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.10 PLL3 and PLL3 Controller The C6472 device includes a PLL3 and a software-programmable PLL3 controller. The PLL3 controller generates the clock. The PLL multiply factor is set to x20 for PLL3.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com expired. The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL3 reset time value, see Table 7-44. The PLL lock time is the amount of time needed from when the PLL is taken out of reset to when the output clock is ready for use. The PLL3 lock time is given in Table 7-44. Table 7-44.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.10.3.1 PLL3 Peripheral ID Register The peripheral identification register (PID) is a constant register that contains the ID and ID revision number for that module. The PID stores version information used to identify the module. All bits within this register are read-only (writes have no effect).
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.10.4 PLL3 Controller Input and Output Clock Electrical Data/Timing Table 7-48. Timing Requirements for CLKIN3 Devices (see Figure 7-37) 500/625/700 PLL MODE x20 NO. UNIT MIN MAX 37.5 50 1 tc(CLKIN3) Cycle time, CLKIN3 2 tw(CLKIN3H) Pulse duration, CLKIN3 high 0.4 * tc(CLKIN3) ns ns 3 tw(CLKIN3L) Pulse duration, CLKIN3 low 0.4 * tc(CLKIN3) ns 4 tt(CLKIN3) Transition time, CLKIN3 1.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.11 DDR2 Memory Controller The 32-bit DDR2 Memory Controller bus of the C6472 is used to interface to JEDEC DDR2 SDRAM devices. The DDR2 bus is designed to sustain a throughput of up to 2.13 GBps at a 533-MHz data rate (267-MHz clock rate) as long as data requests are pending in the DDR2 Memory Controller. The DDR2 external bus only interfaces to DDR2 devices; it does not share the bus with any other types of peripherals. 7.11.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.11.3 DDR2 Memory Controller Electrical Data/Timing The TMS320C6472/TMS320TCI6486 DDR2 Implementation Guidelines application report (literature number SPRAAT7) specifies a complete DDR2 interface solution for the C6472 device as well as a list of compatible DDR2 devices.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.12 I2C Peripheral The inter-integrated circuit (I2C) module provides an interface between a C64x+ DSP and other devices compliant with Philips Semiconductors Inter-IC bus™ (I2C bus) specification version 2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP through the I2C module. 7.12.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.12.2 I2C Peripheral Register Descriptions Table 7-50.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.12.3 I2C Electrical Data/Timing Table 7-51. Timing Requirements for I2C Input (1) (see Figure 7-39) 500/625/700 STANDARD MODE MIN (3) (4) (5) UNIT MIN MAX Cycle time, SCL 10 2.5 μs 2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 μs 3 th(SCLL-SDAL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 4 0.6 μs 4 tw(SCLL) Pulse duration, SCL low 4.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-52. Switching Characteristics Over Recommended Operating Conditions for I2C Output (see Figure 7-40) 500/625/700 NO. PARAMETER STANDARD MODE MIN MAX FAST MODE MIN UNIT MAX tc(SCL) Cycle time, SCL 10 2.5 μs 17 td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) 4.7 0.6 μs 18 td(SDAL-SCLL) Delay time, SDA low to SCL low (for a START and a repeated START condition) 4 0.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.13 Host-Port Interface (HPI) Peripheral 7.13.1 HPI Device-Specific Information The C6472 device includes a user-configurable 16-bit host-port interface (HPI16). A host processor uses HPI to access internal registers and C6472 memory or external memory through the C6472 DDR2 EMIF.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.13.4 HPI Electrical Data/Timing Table 7-54. Timing Requirements for Host-Port Interface Cycles (1) (2) (see Figure 7-41 through Figure 7-44) 500/625/700 NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-55. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface Cycles (1) (2) (3) (see Figure 7-41 through Figure 7-44) PARAMETER Case 1. HPIC or HPIA read 1 td(HSTBL-HDV) Delay time, HSTROBE low to DSP data valid 3 UNIT MAX 20 17 * M + 20 Case 3.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com HCS HAS HCNTL[1:0] HR/W HHWIL 13 16 16 15 15 37 37 14 13 HSTROBE(A) 3 3 1 2 1 2 HD[15:0] 38 PRODUCT PREVIEW 4 7 6 HRDY(B) A. B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com HCS HAS 12 11 12 11 HCNTL[1:0] 12 11 12 11 12 11 12 11 HR/W HHWIL 10 9 10 9 37 13 37 13 14 1 3 2 1 3 PRODUCT PREVIEW HSTROBE(A) 2 HD[15:0] 7 36 6 38 HRDY(B) A. B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com HCS HAS HCNTL[1:0] HR/W HHWIL 16 13 16 15 37 15 37 13 14 HSTROBE(A) 18 18 17 17 HD[15:0] PRODUCT PREVIEW 4 35 38 34 5 34 5 HRDY(B) A. B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com HCS HAS 12 11 12 11 HCNTL[1:0] 12 11 11 12 11 11 12 HR/W 12 HHWIL 9 14 37 HSTROBE(A) 10 37 13 13 18 18 PRODUCT PREVIEW 10 9 17 17 HD[15:0] 34 35 34 5 36 5 38 HRDY(B) A. B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.14 TSIP PRODUCT PREVIEW The TSIP is a multi-link serial interface consisting of a maximum of eight transmit data signals (or links), eight receive data signals (or links), two frame sync input signals, and two serial clock inputs. The TSIP module offers support for a maximum of 1024 timeslots for transmit and receive. Typically, 672 timeslots (DS3) for transmit and receive are utilized on these links.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-58. TDMU Global Registers (continued) HEX ADDRESS RANGE ACRONYM 0250 0114 RBMST 0250 0118 - 0250 017C - REGISTER NAME Receive Channel Active Status Register Reserved Table 7-59.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-61. TX/RX Channels 0-5 Error Registers (continued) HEX ADDRESS RANGE ACRONYM 0250 0254 ERRCNT5 TX/RX Channel 5 Error Count Register REGISTER NAME 0250 0258 ERRQ5 TX/RX Channel 5 Error Queue Register 0250 025C - Reserved Table 7-62.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-64. TDMU Receive Channels 0-5 Registers (continued) HEX ADDRESS RANGE ACRONYM 0250 0C80 RCHEN4 0250 0C84 - 0250 0C9C - 0250 0CA0 RCHEN5 0250 0CA4 - 0250 0CBC - REGISTER NAME Receive Channel 4 Enable Register Reserved Receive Channel 5 Enable Register Reserved Table 7-65.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-66.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-66. DMATCU Transmit Channels 0-5 Registers (continued) HEX ADDRESS RANGE ACRONYM 0250 116C DXCH_BFCNT5 0250 1170 - 0250 117C - REGISTER NAME Transmit Channel 5 Frame Count Register B Reserved Table 7-67.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-67.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-69.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-69. TDMU Channel Buffers (continued) HEX ADDRESS RANGE ACRONYM 0251 AD00 - 0253 FFFC - REGISTER NAME Reserved 7.14.2 TSIP1 Peripheral Register Descriptions Table 7-70. TSIP Module Registers HEX ADDRESS RANGE ACRONYM 0254 0000 PID 0254 0004 EMUTST 0254 0008 RST 0254 000C - 0254 007C - REGISTER NAME PID Register Emulation and Test Register Reset Register Reserved Table 7-71.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-74.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-76. TDMU Channel Registers (continued) HEX ADDRESS RANGE ACRONYM 0254 0C60 - 0254 0C7C - Receive Channel 3 Registers REGISTER NAME 0254 0C80 - 0254 0C9C - Receive Channel 4 Registers 0254 0CA0 - 0254 0CBC - Receive Channel 5 Registers 0254 0CC0 - 0254 0FFC - Reserved Table 7-77.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-79.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-80.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-81.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-81. DMATCU Receive Channels 0-5 Registers (continued) HEX ADDRESS RANGE ACRONYM 0254 196C DRCH _BFCNT5 0254 1970 - 0254 197C - REGISTER NAME Receive Channel 5 Frame Count Register B Reserved Table 7-82.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-83.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.14.3 TSIP2 Peripheral Register Descriptions Table 7-84. TSIP Module Registers HEX ADDRESS RANGE ACRONYM 0258 0000 PID 0258 0004 EMUTST 0258 0008 RST 0258 000C - 0258 007C - REGISTER NAME PID Register Emulation and Test Register Reset Register Reserved Table 7-85.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-88. TDMU Channel Error Registers (continued) HEX ADDRESS RANGE ACRONYM 0258 0240 - 0258 024C - TX/RX Channel 4 Error Log Registers REGISTER NAME 0258 0250 - 0258 025C - TX/RX Channel 5 Error Log Registers 0258 0260 - 0258 03FC - Reserved Table 7-89.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-91.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-93.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-94.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-95.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-96.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-97.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.14.4 TSIP Electrical Data/Timing Table 7-98. Timing Requirements for TSIP 2X Mode (1) (see Figure 7-45) 500/625/700 NO. MIN MAX UNIT 61 (2) ns Pulse duration, CLK low 0.4 tc(clk) ns Pulse duration, CLK high 0.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-99. Timing Requirements for TSIP 1X Mode (1) (see Figure 7-46) 500/625/700 NO. (2) MAX UNIT 11 tc(CLK) Cycle time, CLK rising edge to next CLK rising edge 122.1 (2) ns 12 tw(CLKL) Pulse duration, CLK low 0.4 tc(clk) ns 13 tw(CLKH) Pulse duration, CLK high 0.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.15 Ethernet MAC (EMAC) The C6472 device contains two Ethernet Media Access Controller (EMAC) interfaces. Each EMAC module provides an efficient interface between the C6472 DSP core processor and the networked community.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.15.1 EMAC Device-Specific Information Interface Modes The EMAC module on the TMS320C6472 device supports five interface modes: Media Independent Interface (MII), Reduced Media Independent Interface (RMII), Source Synchronous Serial Media Independent Interface (S3MII), Gigabit Media Independent Interface (GMII), and Reduced Gigabit Media Independent Interface (RGMII). The MII and GMII interface modes are defined in the IEEE 802.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-100.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.15.2 EMAC Peripheral Register Descriptions Table 7-101.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-101.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-101.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-102.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-103.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-103.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-104.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.15.3 EMIC Peripheral Register Descriptions Table 7-105.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.15.4 EMAC Electrical Data/Timing (MII, GMII, RMII, RGMII, and SSMII) 7.15.4.1 EMAC MII and GMII Electrical Data/Timing Table 7-109. Timing Requirements for MRCLK - MII and GMII Operation (see Figure 7-48) 500/625/700 NO. 1000 Mbps MIN 1 tc(MRCLK) Cycle time, MRCLK 2 tw(MRCLKH) 3 4 MAX 100 Mbps 10 Mbps MIN MIN MAX UNIT MAX 8 40 400 ns Pulse duration, MRCLK high 2.8 14 140 ns tw(MRCLKL) Pulse duration, MRCLK low 2.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 1 2 4 3 [G]MTCLK 4 Figure 7-49. [G]MTCLK Timing Table 7-112. Timing Requirements for EMAC MII and GMII Receive 10/100 Mbit/s (see Figure 7-50) 500/625/700 NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-114. Switching Characteristics Over Recommended Operating Conditions for EMAC MII and GMII Transmit 10/100 Mbit/s (see Figure 7-51) 500/625/700 NO. 1 PARAMETER 10/100 Mbps UNIT MIN MAX td(GMII_MTXD) Delay time, GMII_MTCLK rising edge to GMII_MTXD 5 25 td(GMII_MTXEN) Delay time, GMII_MTCLK rising edge to GMII_MTXEN 5 25 ns Table 7-115.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 7.15.4.2 www.ti.com EMAC RMII Electrical Data/Timing The RMREFCLK pin is used to source a clock to the EMAC when it is configured for RMII operation. The RMREFCLK frequency should be 50 MHz ±50 PPM with a duty cycle between 35% and 65%, inclusive. Table 7-116. Timing Requirements for RMREFCLK - RMII Operation (see Figure 7-52) NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.15.4.3 EMAC RGMII Electrical Data/Timing An extra clock signal, RGREFCLK, running at 125 MHz is included as a convenience to the user. Note that this reference clock is not a free-running clock. This should only be used by an external device if it does not expect a valid clock during device reset. Table 7-119. Switching Characteristics Over Recommended Operating Conditions for EMAC RGREFCLK RGMII Operation (see Figure 7-53) NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-120. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Output Operation 10/100/1000 Mbit/s (see Figure 7-54) NO. 1 PARAMETER tc(RGTXC) 500/625/700 SPEED Cycle time, RGTXC MIN 10 Mbps 360 440 100 Mbps 36 44 1000 Mbps 7.2 8.8 10/100 Mbps 0.40*tc(RGTXC) 0.60*tc(RGTXC) 1000 Mbps 0.45*tc(RGTXC) 0.55*tc(RGTXC) 10/100 Mbps 0.40*tc(RGTXC) 0.60*tc(RGTXC) 1000 Mbps 0.45*tc(RGTXC) 0.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-121. Timing Requirements for EMAC RGMII Input Operation 10/100/1000 Mbit/s (see Figure 7-55) 8 9 10 PARAMETER tc(RGRXC) tw(RGRXCH) tw(RGRXCL) 500/625/700 SPEED Cycle time, RGRXC Pulse duration, RGRXC high Pulse duration, RGRXC low MIN 10 Mbps 360 100 Mbps 36 44 1000 Mbps 7.2 8.8 10/100 Mbps 0.40*tc(RGRXC) 0.60*tc(RGRXC) 1000 Mbps 0.45*tc(RGRXC) 0.55*tc(RGRXC) 10/100 Mbps 0.40*tc(RGRXC) 0.60*tc(RGRXC) 0.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.15.4.4 EMAC SSMII Electrical Data/Timing Table 7-122. Timing Requirements for EMAC SSMII Transmit (see Figure 7-56) NO. 500/625/700 PARAMETER MIN TYP MAX 8 UNIT 1 tc(TX_CLK) Cycle time, TX_CLK 2 td(TX_CLK- ns Delay time, TX_CLK high to TX_SYNC output valid 0.5 4.5 ns Delay time, TX_CLK high to TX_DATA output valid 0.5 4.5 ns TX_SYNC) 3 td(TX_CLKTX_DATA) 1 TX_CLK 2 TX_SYNC PRODUCT PREVIEW 3 TX_DATA Figure 7-56.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.15.5 Management Data Input/Output (MDIO) The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.15.5.3 MDIO Electrical Data/Timing Table 7-125. Timing Requirements for MDIO Input (see Figure 7-58) 500/625/700 NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.16 Timers The timers can be used to: time events, count events, generate pulses, interrupt the CPU, and send synchronization events to the EDMA. The localized timers (Timer 0 - Timer 5) can also be used as watchdog timers. 7.16.1 Timer Device-Specific Information The C6472 device has six localized timers (Timer 0 - Timer 5) and six shared timers (Timer 6 - Timer 11).
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-128.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-131.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-134.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-137.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.16.3 Timer Electrical Data/Timing Table 7-139. Timing Requirements for Timer Input (1) (see Figure 7-60) 500/625/700 NO. (1) MIN MAX UNIT 1 tw(TIMIxH) Pulse duration, TIMIxH high 12P ns 2 tw(TIMIxL) Pulse duration, TIMIxL low 12P ns P = 1/CPU clock frequency in ns. Table 7-140. Switching Characteristics Over Recommended Operating Conditions for Timer Output (1) (see Figure 7-60) 500/625/700 NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.17 UTOPIA 7.17.1 UTOPIA Device-Specific Information The Universal Test and Operations PHY Interface for ATM (UTOPIA) peripheral is a 50 MHz, 8-/16-Bit Slave-only interface. The UTOPIA peripheral contains two, two-cell FIFOs, one for transmit and one for receive, to buffer data sent/received at the interface. There is a transmit and a receive indication to the PDMA to enable servicing.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-143.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.17.3 UTOPIA Electrical Data/Timing Table 7-145. Timing Requirements for UTOPIA Receive/Transmit Clock (UCLK) (1) (see Figure 7-62) 500/625/700 NO. (1) MIN MAX 20 UNIT 1 tc(UCLK) UXCLK or URCLK cycle time ns 2 tw(UCLKL) UXCLK or URCLK pulse duration low 0.4tc(URCLK) 0.6tc(URCLK) ns 3 tw(UCLKH) UXCLK or URCLK pulse duration high 0.4tc(URCLK) 0.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-146. Timing Requirements for UTOPIA Slave Receive Cycles (see Figure 7-63) 500/625/700 NO.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-148. Timing Requirements for UTOPIA Slave Transmit Cycles (see Figure 7-64) 500/625/700 NO. MIN UNIT MAX 16 tsu(UXADDR-UXCLKH) Setup time, UXADDR valid before UXCLK high 4 ns 17 th(UXCLKH-UXADDR) Hold time, UXADDR valid after UXCLK high 1 ns 18 tsu(UXENB-UXCLKH) Setup time, UXENB valid before UXCLK high 4 ns 19 th(UXCLKH-UXENB) Hold time, UXENB valid after UXCLK high 1 ns Table 7-149.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.18 Serial RapidIO (SRIO) Port The SRIO ports on the C6472 device are high-performance, low-pin-count interconnects aimed for embedded markets. The use of the RapidIO interconnect in a system board design can create a homogeneous interconnect environment providing simple, high-throughput connectivity and control among the devices.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-150.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-150.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-150.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-150.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-150.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-150.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-150.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-150.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-150.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-150.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.19 General-Purpose Input/Output (GPIO) 7.19.1 GPIO Device-Specific Information On the C6472 device, the GPIO peripheral pins are muxed with configuration inputs that are captured at device reset. For more detailed information on device/peripheral configuration and the C6472 device pin muxing, see Section 3, Device Configuration. 7.19.2 GPIO Peripheral Register Descriptions Table 7-151.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com Table 7-153. Switching Characteristics Over Recommended Operating Conditions for General-Purpose Output (1) (see Figure 7-66) 500/625/700 NO. (1) MIN MAX UNIT 3 tw(GPOH) Pulse duration, GPOx high 6P ns 4 tw(GPOL) Pulse duration, GPOx low 6P ns P = 1/CPU clock frequency in ns. 4 3 GPOx Figure 7-66.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.20 Emulation Features and Capability 7.20.1 Advanced Event Triggering (AET) The C6472 device supports Advanced Event Triggering (AET). This capability can be used to debug complex problems as well as understand performance characteristics of user applications.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.20.3 IEEE 1149.1 JTAG The JTAG interface is used to support boundary scan testing and emulation of the C6472 device. The JTAG interface provides an asynchronous TRST and only the four primary JTAG signals (TCK, TDI, TMS, and TDO) are required for boundary scan. The pins EMU0 and EMU1 have no effect on the operation of the JTAG interface on the C6472 device. Most interfaces on the device follow the Boundary Scan Test Specification (IEEE1149.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 7.20.3.3 JTAG Electrical Data/Timing Table 7-155. Timing Requirements for JTAG (see Figure 7-68) 500/625/700 NO. 1 tc(TCLK) Cycle time, TCLK 3 tsu(TDIV-TCLKH) Setup time, TDI/TMS/TRST valid before TCLK high 4 (1) (2) th(TCLKH-TDIV) Hold time, TDI/TMS/TRST valid after TCLK high MIN MAX 23.255 (1) 6 UNIT ns 3 ns (2) ns Fully-synchronous design removes maximum clock period limitations. Hold time measured from rising edge.
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TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com 8 Mechanical Data 8.1 Thermal Data Table 8-1 shows the thermal resistance characteristics for the PBGA - CTZ/ZTZ mechanical package. Table 8-1. Thermal Resistance Characteristics (S-PBGA Package) [CTZ/ZTZ] NO. 1 RΘJC Junction-to-case 2 RΘJB Junction-to-board 0.56 N/A 5.1 N/A 12.9 0 4 9.9 150 8.5 250 7.3 500 0.027 0 0.028 150 0.028 250 0.029 500 RΘJA Junction-to-free air 6 7 PRODUCT PREVIEW 8.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 13-Feb-2014 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.