Datasheet

Index-2
P
PCI, information for 2.2 standard 2-5
PCI Emulator Dimensions, illustration of 2-2
Pin Dimensions, for the Target Header 3-4
Processors, configuring system clocks 3-14
S
Signal Connections
buffered, illustration of 3-13
unbuffered, illustration of 3-12
signals
EMU, bank selection of 3-17
EMU0−EMU1, considerations 3-16
for JTAG connections 3-2
Standard TAP Controller JTAG 3-2
TI Advance Emulation 3-3
XDS560 Connection 3-2
Specifications
environmental 2-4
mechanical 2-2
physical 2-5
Standards, for the IEEE 1149.1 3-5
T
Target Header, pin dimensions 3-4
Target Header Dimensions, illustration of 2-4
Target System
clocks 3-14
emulation connector 3-4
in connection with the emulator 3-12
Target−System Clock
genereated test, illustration of 3-14
multiple processors, configuring 3-14
Timing Calculations 3-10
Timing Parameters 3-9
Timing Paths, key
case 1 3-10
case 2 3-11
Timing Waveforms 3-9
X
XDS560
bus protocol 3-6
Cable and Pod Dimensions, illustration of 2-3
cable pod logic 3-7
connection signals 3-2
emulation signals 3-2
Emulator Cable Pod Signal Timing 3-9
environmental specifications 2-4
installation 2-6
mechanical specifications 2-2
PCI 2-5
PCI Emulator Dimensions, image of 2-2
physical specifications 2-5
Standards, for the IEEE 1149.1 3-5
Target Header Dimensions, illustration of 2-4