Datasheet

Index-1
Index
B
Buffering Signals 3-12
Bus Protocol, IEEE 1149.1 3-6
C
Cable and Pod Dimensions, illustration of 2-3
Cable/Pod
logic 3-7
signal timing 3-9
timing parameters 3-9
timing waveforms, illustration of 3-9
Cable/Pod Interface, JTAG, illustration of 3-8
Clocks, target system 3-14
generated test 3-14
Connections
between the emulator and target system 3-12
buffering signals 3-12
buffered signals, illustration of 3-13
multiprocessor, illustration of 3-15
unbuffered signals, illustration of 3-12
D
Design Practices, importance of 3-13
E
EMU, signals, banks selection of 3-17
EMU0−EMU1
calculating lines that don’t support HS−
RTDX 3-16
considerations 3-16
emulation signals 3-2
TI Advanced 3-3
Emulator, in connection with the target sys-
tem 3-12
Emulator Connector, for the Target System 3-4
F
XDS560, Features 1-2
H
Header Parts 3-4
HS−RTDX, calculating EMU0−EMU1 lines when not
supported 3-16
I
IEEE 1149.1
bus protocol 3-6
standards 3-5
Installation, XDS560 2-6
J
JTAG
cable/pod interface, illustration of 3-8
emulation signals 3-2
M
Mechanical Dimensions 2-2
Multiprocessor Connections, illustration of 3-15