Datasheet

XDS560 Emulator Cable Pod Signal Timing
3-9
Target Design Considerations for Using the XDS560 Emulation Pod
3.6 XDS560 Emulator Cable Pod Signal Timing
Figure 3−3 shows the default timing waveforms for the XDS560 emulator
cable pod. Table 3−5 defines the timing parameters. These timing parameters
are calculated from values specified in the standard data sheets for the emula-
tor and cable pod and are for reference only.
The presented timing parameters are calculated for the end of the 14-pin tar-
get cable header. Texas Instruments does not test or guarantee these timings.
The XDS560 emulator cable pod uses TCK_RET as its clock source for inter-
nal synchronization. TCK is provided as an optional target system test-clock
source.
Figure 3−3. XDS560 Emulator Cable Pod Timing Waveforms
1
2
3
4 5
6
TCK_RET
TMS/TDI
TDO
Table 3−5. Emulator Cable Pod Timing Parameters
No. Reference Description Min Max Units
1 t
c(TCK)
Cycle time, TCK_RET 20 ns
2t
w(TCKH)
Pulse duration, TCK_RET high 10 ns
3t
w(TCKL)
Pulse duration, TCK_RET low 10 ns
4t
pd(TMS-TDI)
Delay time, TMS/TDI valid from TCK_RET high 18 31 ns
5T
su(TDO)
Setup time, TDO valid before TCK_RET high 2.5 ns
6
T
hd(TDO)
Hold time, TDO valid after TCK_RET high 0 ns
Note: The delay time for TMS/TDI valid in calculated for the default rising edge TCK_RET. The delay time for TMS/TDI valid for
a falling edge TCK_RET configuration is very similar.