Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B

SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014

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3.16.4 AIO_MUX2

The 12 pins of AIO_MUX2 can be selectively mapped through a dedicated set of registers to 12 analog

inputs for ADC2 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or

four General-Purpose Outputs. Note that while AIO_MUX2 has been named after the analog signals

passing through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in

the GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the

AIO_MUX2 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX2

block is programmed through a separate set of registers from those used to program AIO_MUX1.

The multiple registers responsible for configuring the AIO_MUX2 pins are accessible by the C28x CPU

only. The bottom portion of Figure 3-17 shows Control Subsystem registers and muxing logic for the

associated 12 AIO pins. The AIOMUX2 register selects 1 of 12 possible analog input signals or 1 of 6

general-purpose AIO inputs. Other registers allow reading and writing of the 6 AIO bits, as well as setting

the direction for each of the bits (read or write). See Table 3-33 for the mapping of analog inputs and AIOs

to the 12 pins of AIO_MUX2. Peripheral Modes 1 and 2 are currently not available.

AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX2 register to ‘0’. AIO Mode 1 is chosen

by setting selected odd bits of the AIOMUX2 register to ‘1’. For example, setting bit 9 of the AIOMUX2

enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX2 register are

“don’t cares”.

Table 3-33. AIO_MUX2 Pin Assignments (C28x AIO Modes)

(1)(2)

Device Pin Name C28x AIO Mode 0

(3)

C28x AIO Mode 1

(4)

ADC2INA0 – ADC2INA0

ADC2INA2 AIO18 ADC2INA2, COMPA4

ADC2INA3 – ADC2INA3

ADC2INA4 AIO20 ADC2INA4, COMPA5

ADC2INA6 AIO22 ADC2INA6, COMPA6

ADC2INA7 – ADC2INA7

ADC2INB0 – ADC2INB0

ADC2INB2 AIO26 ADC2INB2, COMPB4

ADC2INB3 – ADC2INB3

ADC2INB4 AIO28 ADC2INB4, COMPB5

ADC2INB6 AIO30 ADC2INB6, COMPB6

ADC2INB7 – ADC2INB7

(1) Blank fields represent Reserved functions.

(2) For each field with two pins (for example, ADC2INA6, COMPA6), only one pin should be enabled at a time; the other pin should be

disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs.

(3) AIO Mode 0 represents digital general-purpose inputs or outputs.

(4) AIO Mode 1 represents analog inputs for ADC2 or the Comparator module.

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