Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B

SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014

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3.12.3 C28x STANDBY Mode

In STANDBY Mode, the C28x processor stops executing instructions and the C28CLKIN, C28CPUCLK,

and C28SYSCLK are turned off. Exit from STANDBY Mode is accomplished by one of 64 GPIOs from the

GPIO_MUX1 block, or MTOCIPCINT1 (interrupt from MTOC IPC peripheral). The wakeup GPIO selected

inside the GPIO_MUX block enters the Qualification Block as the LPMWAKE signal. Inside the

Qualification Block, the LPMWAKE signal is sampled per the QUALSTDBY bits (bits [7:2] of the

CPCLKCR0 register) before propagating into the wake request logic.

Cortex-M3 should use CLPMSTAT register bits to tell the C28x to go into STANDBY mode before going

into Deep Sleep mode. Otherwise, the clock to the C28x will be turned off suddenly when the control

software is not expecting this clock to shut off. When the device is in Deep Sleep/STANDBY mode, wake-

up should happen only from the Master Subsystem, since all C28x clocks are off (C28CLKIN,

C28CPUCLK, C28SYSCLK), thus preventing the C28x from waking up first.

Upon exit from STANDBY Mode, the C28CLKIN, C28SYSCLK, and C28CPUCLK are restored. If the

LPMWAKE interrupt is enabled, the LPMWAKE ISR is executed. Next, the C28x processor starts fetching

instructions from a location immediately following the IDLE instruction that originally triggered the

STANDBY Mode.

NOTE

For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function

is available on silicon revision 0 devices (GPIO and other functions listed in Table 4-1 are not

available).

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