Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
3.11.1 Cortex-M3 Run Mode
In Run Mode, the Cortex-M3 processor, memory, and most of the peripherals are clocked by the
M3SSCLK, which is a divide-down version of the PLLSYSCLK (from Main PLL). The USB is clocked from
a dedicated USB PLL, the CAN peripherals are clocked by M3SSCLK, OSCCLK, or XCLKIN, and one of
two watchdogs (WDOG1) is also clocked by the OSCCLK. Clock selection for these peripherals is
accomplished via corresponding peripheral configuration registers. Clock gating for individual peripherals
is defined inside the RCGS register. RCGS, SCGS, and DCGS clock-gating settings only apply to
peripherals that are enabled in a corresponding DC (Device Configuration) register.
Execution of the WFI instruction (Wait-for-Interrupt) shuts down the HCLK to the Cortex-M3 CPU and
forces the Cortex-M3 Subsystem into Sleep or Deep Sleep low-power mode, depending on the state of
the SLEEPDEEP bit of the Cortex-M3 SYSCTRL register. To come out of a low-power mode, any properly
configured interrupt event terminates the Sleep or Deep Sleep Mode and returns the Cortex-M3
processor/subsystem to Run Mode.
3.11.2 Cortex-M3 Sleep Mode
In Sleep Mode, the Cortex-M3 processor and memory are prevented from clocking, and thus the code is
no longer executing. The gating for the peripheral clocks may change based on the ACG bit of the RCC
register. When ACG = 0, the peripheral clock gating is used as defined by the RCGS registers (same as in
Run Mode); and when ASC = 1, the clock gating comes from the SCGS register. RCGS and SCGS clock-
gating settings only apply to peripherals that are enabled in a corresponding DC register. Peripheral clock
frequency for the enabled peripherals in Sleep Mode is the same as during the Run Mode.
Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Sleep Mode
depends on the SLEEPEXIT bit of the SYSCTRL register. When the SLEEPEXIT bit is 1, the processor
will temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up. After that,
the processor goes back to Sleep Mode. When the SLEEPEXIT bit is 0, the processor wakes up
permanently (for the ISR and thereafter).
58 Device Overview Copyright © 2012–2014, Texas Instruments Incorporated
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